1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_gic.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <generic_delay_timer.h> 13 #include <mmio.h> 14 #include <platform.h> 15 #include <plat_private.h> 16 #include <platform_def.h> 17 18 /******************************************************************************* 19 * Declarations of linker defined symbols which will help us find the layout 20 * of trusted SRAM 21 ******************************************************************************/ 22 unsigned long __RO_START__; 23 unsigned long __RO_END__; 24 25 /* 26 * The next 2 constants identify the extents of the code & RO data region. 27 * These addresses are used by the MMU setup code and therefore they must be 28 * page-aligned. It is the responsibility of the linker script to ensure that 29 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 30 */ 31 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 32 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 33 34 static entry_point_info_t bl32_ep_info; 35 static entry_point_info_t bl33_ep_info; 36 37 /******************************************************************************* 38 * Return a pointer to the 'entry_point_info' structure of the next image for 39 * the security state specified. BL33 corresponds to the non-secure image type 40 * while BL32 corresponds to the secure image type. A NULL pointer is returned 41 * if the image does not exist. 42 ******************************************************************************/ 43 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 44 { 45 entry_point_info_t *next_image_info; 46 47 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 48 49 /* None of the images on this platform can have 0x0 as the entrypoint */ 50 if (next_image_info->pc) 51 return next_image_info; 52 else 53 return NULL; 54 } 55 56 /******************************************************************************* 57 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 58 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they 59 * are lost (potentially). This needs to be done before the MMU is initialized 60 * so that the memory layout can be used while creating page tables. 61 * BL2 has flushed this information to memory, so we are guaranteed to pick up 62 * good data. 63 ******************************************************************************/ 64 void bl31_early_platform_setup(bl31_params_t *from_bl2, 65 void *plat_params_from_bl2) 66 { 67 console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK, 68 PLAT_RK_UART_BAUDRATE); 69 70 VERBOSE("bl31_setup\n"); 71 72 /* Passing a NULL context is a critical programming error */ 73 assert(from_bl2); 74 75 assert(from_bl2->h.type == PARAM_BL31); 76 assert(from_bl2->h.version >= VERSION_1); 77 78 bl32_ep_info = *from_bl2->bl32_ep_info; 79 bl33_ep_info = *from_bl2->bl33_ep_info; 80 81 plat_rockchip_pmusram_prepare(); 82 83 /* there may have some board sepcific message need to initialize */ 84 params_early_setup(plat_params_from_bl2); 85 } 86 87 /******************************************************************************* 88 * Perform any BL3-1 platform setup code 89 ******************************************************************************/ 90 void bl31_platform_setup(void) 91 { 92 generic_delay_timer_init(); 93 plat_rockchip_soc_init(); 94 95 /* Initialize the gic cpu and distributor interfaces */ 96 plat_rockchip_gic_driver_init(); 97 plat_rockchip_gic_init(); 98 plat_rockchip_pmu_init(); 99 } 100 101 /******************************************************************************* 102 * Perform the very early platform specific architectural setup here. At the 103 * moment this is only intializes the mmu in a quick and dirty way. 104 ******************************************************************************/ 105 void bl31_plat_arch_setup(void) 106 { 107 plat_cci_init(); 108 plat_cci_enable(); 109 plat_configure_mmu_el3(BL31_RO_BASE, 110 BL_COHERENT_RAM_END - BL31_RO_BASE, 111 BL31_RO_BASE, 112 BL31_RO_LIMIT, 113 BL_COHERENT_RAM_BASE, 114 BL_COHERENT_RAM_END); 115 } 116