1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <string.h> 8 #include <stdint.h> 9 #include <dram.h> 10 #include <utils.h> 11 #include "dram_spec_timing.h" 12 13 static const uint8_t ddr3_cl_cwl[][7] = { 14 /* 15 * speed 0~330 331 ~ 400 401 ~ 533 534~666 667~800 801~933 934~1066 16 * tCK>3 2.5~3 1.875~2.5 1.5~1.875 1.25~1.5 1.07~1.25 0.938~1.07 17 * cl<<4, cwl cl<<4, cwl cl<<4, cwl 18 */ 19 /* DDR3_800D (5-5-5) */ 20 {((5 << 4) | 5), ((5 << 4) | 5), 0, 0, 0, 0, 0}, 21 /* DDR3_800E (6-6-6) */ 22 {((5 << 4) | 5), ((6 << 4) | 5), 0, 0, 0, 0, 0}, 23 /* DDR3_1066E (6-6-6) */ 24 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), 0, 0, 0, 0}, 25 /* DDR3_1066F (7-7-7) */ 26 {((5 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), 0, 0, 0, 0}, 27 /* DDR3_1066G (8-8-8) */ 28 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), 0, 0, 0, 0}, 29 /* DDR3_1333F (7-7-7) */ 30 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 31 0, 0, 0}, 32 /* DDR3_1333G (8-8-8) */ 33 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 34 0, 0, 0}, 35 /* DDR3_1333H (9-9-9) */ 36 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((9 << 4) | 7), 37 0, 0, 0}, 38 /* DDR3_1333J (10-10-10) */ 39 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 40 0, 0, 0}, 41 /* DDR3_1600G (8-8-8) */ 42 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 43 ((8 << 4) | 8), 0, 0}, 44 /* DDR3_1600H (9-9-9) */ 45 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 46 ((9 << 4) | 8), 0, 0}, 47 /* DDR3_1600J (10-10-10) */ 48 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 49 ((10 << 4) | 8), 0, 0}, 50 /* DDR3_1600K (11-11-11) */ 51 {((5 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 52 ((11 << 4) | 8), 0, 0}, 53 /* DDR3_1866J (10-10-10) */ 54 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 55 ((9 << 4) | 8), ((11 << 4) | 9), 0}, 56 /* DDR3_1866K (11-11-11) */ 57 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((8 << 4) | 7), 58 ((10 << 4) | 8), ((11 << 4) | 9), 0}, 59 /* DDR3_1866L (12-12-12) */ 60 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 61 ((11 << 4) | 8), ((12 << 4) | 9), 0}, 62 /* DDR3_1866M (13-13-13) */ 63 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 64 ((11 << 4) | 8), ((13 << 4) | 9), 0}, 65 /* DDR3_2133K (11-11-11) */ 66 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((7 << 4) | 7), 67 ((9 << 4) | 8), ((10 << 4) | 9), ((11 << 4) | 10)}, 68 /* DDR3_2133L (12-12-12) */ 69 {((5 << 4) | 5), ((5 << 4) | 5), ((6 << 4) | 6), ((8 << 4) | 7), 70 ((9 << 4) | 8), ((11 << 4) | 9), ((12 << 4) | 10)}, 71 /* DDR3_2133M (13-13-13) */ 72 {((5 << 4) | 5), ((5 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 73 ((10 << 4) | 8), ((12 << 4) | 9), ((13 << 4) | 10)}, 74 /* DDR3_2133N (14-14-14) */ 75 {((6 << 4) | 5), ((6 << 4) | 5), ((7 << 4) | 6), ((9 << 4) | 7), 76 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)}, 77 /* DDR3_DEFAULT */ 78 {((6 << 4) | 5), ((6 << 4) | 5), ((8 << 4) | 6), ((10 << 4) | 7), 79 ((11 << 4) | 8), ((13 << 4) | 9), ((14 << 4) | 10)} 80 }; 81 82 static const uint16_t ddr3_trc_tfaw[] = { 83 /* tRC tFAW */ 84 ((50 << 8) | 50), /* DDR3_800D (5-5-5) */ 85 ((53 << 8) | 50), /* DDR3_800E (6-6-6) */ 86 87 ((49 << 8) | 50), /* DDR3_1066E (6-6-6) */ 88 ((51 << 8) | 50), /* DDR3_1066F (7-7-7) */ 89 ((53 << 8) | 50), /* DDR3_1066G (8-8-8) */ 90 91 ((47 << 8) | 45), /* DDR3_1333F (7-7-7) */ 92 ((48 << 8) | 45), /* DDR3_1333G (8-8-8) */ 93 ((50 << 8) | 45), /* DDR3_1333H (9-9-9) */ 94 ((51 << 8) | 45), /* DDR3_1333J (10-10-10) */ 95 96 ((45 << 8) | 40), /* DDR3_1600G (8-8-8) */ 97 ((47 << 8) | 40), /* DDR3_1600H (9-9-9)*/ 98 ((48 << 8) | 40), /* DDR3_1600J (10-10-10) */ 99 ((49 << 8) | 40), /* DDR3_1600K (11-11-11) */ 100 101 ((45 << 8) | 35), /* DDR3_1866J (10-10-10) */ 102 ((46 << 8) | 35), /* DDR3_1866K (11-11-11) */ 103 ((47 << 8) | 35), /* DDR3_1866L (12-12-12) */ 104 ((48 << 8) | 35), /* DDR3_1866M (13-13-13) */ 105 106 ((44 << 8) | 35), /* DDR3_2133K (11-11-11) */ 107 ((45 << 8) | 35), /* DDR3_2133L (12-12-12) */ 108 ((46 << 8) | 35), /* DDR3_2133M (13-13-13) */ 109 ((47 << 8) | 35), /* DDR3_2133N (14-14-14) */ 110 111 ((53 << 8) | 50) /* DDR3_DEFAULT */ 112 }; 113 114 static uint32_t get_max_speed_rate(struct timing_related_config *timing_config) 115 { 116 if (timing_config->ch_cnt > 1) 117 return max(timing_config->dram_info[0].speed_rate, 118 timing_config->dram_info[1].speed_rate); 119 else 120 return timing_config->dram_info[0].speed_rate; 121 } 122 123 static uint32_t 124 get_max_die_capability(struct timing_related_config *timing_config) 125 { 126 uint32_t die_cap = 0; 127 uint32_t cs, ch; 128 129 for (ch = 0; ch < timing_config->ch_cnt; ch++) { 130 for (cs = 0; cs < timing_config->dram_info[ch].cs_cnt; cs++) { 131 die_cap = max(die_cap, 132 timing_config-> 133 dram_info[ch].per_die_capability[cs]); 134 } 135 } 136 return die_cap; 137 } 138 139 /* tRSTL, 100ns */ 140 #define DDR3_TRSTL (100) 141 /* trsth, 500us */ 142 #define DDR3_TRSTH (500000) 143 /* trefi, 7.8us */ 144 #define DDR3_TREFI_7_8_US (7800) 145 /* tWR, 15ns */ 146 #define DDR3_TWR (15) 147 /* tRTP, max(4 tCK,7.5ns) */ 148 #define DDR3_TRTP (7) 149 /* tRRD = max(4nCK, 10ns) */ 150 #define DDR3_TRRD (10) 151 /* tCK */ 152 #define DDR3_TCCD (4) 153 /*tWTR, max(4 tCK,7.5ns)*/ 154 #define DDR3_TWTR (7) 155 /* tCK */ 156 #define DDR3_TRTW (0) 157 /* tRAS, 37.5ns(400MHz) 37.5ns(533MHz) */ 158 #define DDR3_TRAS (37) 159 /* ns */ 160 #define DDR3_TRFC_512MBIT (90) 161 /* ns */ 162 #define DDR3_TRFC_1GBIT (110) 163 /* ns */ 164 #define DDR3_TRFC_2GBIT (160) 165 /* ns */ 166 #define DDR3_TRFC_4GBIT (300) 167 /* ns */ 168 #define DDR3_TRFC_8GBIT (350) 169 170 /*pd and sr*/ 171 #define DDR3_TXP (7) /* tXP, max(3 tCK, 7.5ns)( < 933MHz) */ 172 #define DDR3_TXPDLL (24) /* tXPDLL, max(10 tCK, 24ns) */ 173 #define DDR3_TDLLK (512) /* tXSR, tDLLK=512 tCK */ 174 #define DDR3_TCKE_400MHZ (7) /* tCKE, max(3 tCK,7.5ns)(400MHz) */ 175 #define DDR3_TCKE_533MHZ (6) /* tCKE, max(3 tCK,5.625ns)(533MHz) */ 176 #define DDR3_TCKSRE (10) /* tCKSRX, max(5 tCK, 10ns) */ 177 178 /*mode register timing*/ 179 #define DDR3_TMOD (15) /* tMOD, max(12 tCK,15ns) */ 180 #define DDR3_TMRD (4) /* tMRD, 4 tCK */ 181 182 /* ZQ */ 183 #define DDR3_TZQINIT (640) /* tZQinit, max(512 tCK, 640ns) */ 184 #define DDR3_TZQCS (80) /* tZQCS, max(64 tCK, 80ns) */ 185 #define DDR3_TZQOPER (320) /* tZQoper, max(256 tCK, 320ns) */ 186 187 /* Write leveling */ 188 #define DDR3_TWLMRD (40) /* tCK */ 189 #define DDR3_TWLO (9) /* max 7.5ns */ 190 #define DDR3_TWLDQSEN (25) /* tCK */ 191 192 /* 193 * Description: depend on input parameter "timing_config", 194 * and calculate all ddr3 195 * spec timing to "pdram_timing" 196 * parameters: 197 * input: timing_config 198 * output: pdram_timing 199 */ 200 static void ddr3_get_parameter(struct timing_related_config *timing_config, 201 struct dram_timing_t *pdram_timing) 202 { 203 uint32_t nmhz = timing_config->freq; 204 uint32_t ddr_speed_bin = get_max_speed_rate(timing_config); 205 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 206 uint32_t tmp; 207 208 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 209 pdram_timing->mhz = nmhz; 210 pdram_timing->al = 0; 211 pdram_timing->bl = timing_config->bl; 212 if (nmhz <= 330) 213 tmp = 0; 214 else if (nmhz <= 400) 215 tmp = 1; 216 else if (nmhz <= 533) 217 tmp = 2; 218 else if (nmhz <= 666) 219 tmp = 3; 220 else if (nmhz <= 800) 221 tmp = 4; 222 else if (nmhz <= 933) 223 tmp = 5; 224 else 225 tmp = 6; 226 227 /* when dll bypss cl = cwl = 6 */ 228 if (nmhz < 300) { 229 pdram_timing->cl = 6; 230 pdram_timing->cwl = 6; 231 } else { 232 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; 233 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; 234 } 235 236 switch (timing_config->dramds) { 237 case 40: 238 tmp = DDR3_DS_40; 239 break; 240 case 34: 241 default: 242 tmp = DDR3_DS_34; 243 break; 244 } 245 246 if (timing_config->odt) 247 switch (timing_config->dramodt) { 248 case 60: 249 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_60; 250 break; 251 case 40: 252 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_40; 253 break; 254 case 120: 255 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_120; 256 break; 257 case 0: 258 default: 259 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 260 break; 261 } 262 else 263 pdram_timing->mr[1] = tmp | DDR3_RTT_NOM_DIS; 264 265 pdram_timing->mr[2] = DDR3_MR2_CWL(pdram_timing->cwl); 266 pdram_timing->mr[3] = 0; 267 268 pdram_timing->trstl = ((DDR3_TRSTL * nmhz + 999) / 1000); 269 pdram_timing->trsth = ((DDR3_TRSTH * nmhz + 999) / 1000); 270 /* tREFI, average periodic refresh interval, 7.8us */ 271 pdram_timing->trefi = ((DDR3_TREFI_7_8_US * nmhz + 999) / 1000); 272 /* base timing */ 273 pdram_timing->trcd = pdram_timing->cl; 274 pdram_timing->trp = pdram_timing->cl; 275 pdram_timing->trppb = pdram_timing->cl; 276 tmp = ((DDR3_TWR * nmhz + 999) / 1000); 277 pdram_timing->twr = tmp; 278 pdram_timing->tdal = tmp + pdram_timing->trp; 279 if (tmp < 9) { 280 tmp = tmp - 4; 281 } else { 282 tmp += (tmp & 0x1) ? 1 : 0; 283 tmp = tmp >> 1; 284 } 285 if (pdram_timing->bl == 4) 286 pdram_timing->mr[0] = DDR3_BC4 287 | DDR3_CL(pdram_timing->cl) 288 | DDR3_WR(tmp); 289 else 290 pdram_timing->mr[0] = DDR3_BL8 291 | DDR3_CL(pdram_timing->cl) 292 | DDR3_WR(tmp); 293 tmp = ((DDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 294 pdram_timing->trtp = max(4, tmp); 295 pdram_timing->trc = 296 (((ddr3_trc_tfaw[ddr_speed_bin] >> 8) * nmhz + 999) / 1000); 297 tmp = ((DDR3_TRRD * nmhz + 999) / 1000); 298 pdram_timing->trrd = max(4, tmp); 299 pdram_timing->tccd = DDR3_TCCD; 300 tmp = ((DDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 301 pdram_timing->twtr = max(4, tmp); 302 pdram_timing->trtw = DDR3_TRTW; 303 pdram_timing->tras_max = 9 * pdram_timing->trefi; 304 pdram_timing->tras_min = ((DDR3_TRAS * nmhz + (nmhz >> 1) + 999) 305 / 1000); 306 pdram_timing->tfaw = 307 (((ddr3_trc_tfaw[ddr_speed_bin] & 0x0ff) * nmhz + 999) 308 / 1000); 309 /* tRFC, 90ns(512Mb),110ns(1Gb),160ns(2Gb),300ns(4Gb),350ns(8Gb) */ 310 if (ddr_capability_per_die <= 0x4000000) 311 tmp = DDR3_TRFC_512MBIT; 312 else if (ddr_capability_per_die <= 0x8000000) 313 tmp = DDR3_TRFC_1GBIT; 314 else if (ddr_capability_per_die <= 0x10000000) 315 tmp = DDR3_TRFC_2GBIT; 316 else if (ddr_capability_per_die <= 0x20000000) 317 tmp = DDR3_TRFC_4GBIT; 318 else 319 tmp = DDR3_TRFC_8GBIT; 320 pdram_timing->trfc = (tmp * nmhz + 999) / 1000; 321 pdram_timing->txsnr = max(5, (((tmp + 10) * nmhz + 999) / 1000)); 322 pdram_timing->tdqsck_max = 0; 323 /*pd and sr*/ 324 pdram_timing->txsr = DDR3_TDLLK; 325 tmp = ((DDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 326 pdram_timing->txp = max(3, tmp); 327 tmp = ((DDR3_TXPDLL * nmhz + 999) / 1000); 328 pdram_timing->txpdll = max(10, tmp); 329 pdram_timing->tdllk = DDR3_TDLLK; 330 if (nmhz >= 533) 331 tmp = ((DDR3_TCKE_533MHZ * nmhz + 999) / 1000); 332 else 333 tmp = ((DDR3_TCKE_400MHZ * nmhz + (nmhz >> 1) + 999) / 1000); 334 pdram_timing->tcke = max(3, tmp); 335 pdram_timing->tckesr = (pdram_timing->tcke + 1); 336 tmp = ((DDR3_TCKSRE * nmhz + 999) / 1000); 337 pdram_timing->tcksre = max(5, tmp); 338 pdram_timing->tcksrx = max(5, tmp); 339 /*mode register timing*/ 340 tmp = ((DDR3_TMOD * nmhz + 999) / 1000); 341 pdram_timing->tmod = max(12, tmp); 342 pdram_timing->tmrd = DDR3_TMRD; 343 pdram_timing->tmrr = 0; 344 /*ODT*/ 345 pdram_timing->todton = pdram_timing->cwl - 2; 346 /*ZQ*/ 347 tmp = ((DDR3_TZQINIT * nmhz + 999) / 1000); 348 pdram_timing->tzqinit = max(512, tmp); 349 tmp = ((DDR3_TZQCS * nmhz + 999) / 1000); 350 pdram_timing->tzqcs = max(64, tmp); 351 tmp = ((DDR3_TZQOPER * nmhz + 999) / 1000); 352 pdram_timing->tzqoper = max(256, tmp); 353 /* write leveling */ 354 pdram_timing->twlmrd = DDR3_TWLMRD; 355 pdram_timing->twldqsen = DDR3_TWLDQSEN; 356 pdram_timing->twlo = ((DDR3_TWLO * nmhz + (nmhz >> 1) + 999) / 1000); 357 } 358 359 #define LPDDR2_TINIT1 (100) /* ns */ 360 #define LPDDR2_TINIT2 (5) /* tCK */ 361 #define LPDDR2_TINIT3 (200000) /* 200us */ 362 #define LPDDR2_TINIT4 (1000) /* 1us */ 363 #define LPDDR2_TINIT5 (10000) /* 10us */ 364 #define LPDDR2_TRSTL (0) /* tCK */ 365 #define LPDDR2_TRSTH (500000) /* 500us */ 366 #define LPDDR2_TREFI_3_9_US (3900) /* 3.9us */ 367 #define LPDDR2_TREFI_7_8_US (7800) /* 7.8us */ 368 369 /* base timing */ 370 #define LPDDR2_TRCD (24) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 371 #define LPDDR2_TRP_PB (18) /* tRPpb,15ns(Fast)18ns(Typ)24ns(Slow) */ 372 #define LPDDR2_TRP_AB_8_BANK (21) /* tRPab,18ns(Fast)21ns(Typ)27ns(Slow) */ 373 #define LPDDR2_TWR (15) /* tWR, max(3tCK,15ns) */ 374 #define LPDDR2_TRTP (7) /* tRTP, max(2tCK, 7.5ns) */ 375 #define LPDDR2_TRRD (10) /* tRRD, max(2tCK,10ns) */ 376 #define LPDDR2_TCCD (2) /* tCK */ 377 #define LPDDR2_TWTR_GREAT_200MHZ (7) /* ns */ 378 #define LPDDR2_TWTR_LITTLE_200MHZ (10) /* ns */ 379 #define LPDDR2_TRTW (0) /* tCK */ 380 #define LPDDR2_TRAS_MAX (70000) /* 70us */ 381 #define LPDDR2_TRAS (42) /* tRAS, max(3tCK,42ns) */ 382 #define LPDDR2_TFAW_GREAT_200MHZ (50) /* max(8tCK,50ns) */ 383 #define LPDDR2_TFAW_LITTLE_200MHZ (60) /* max(8tCK,60ns) */ 384 #define LPDDR2_TRFC_8GBIT (210) /* ns */ 385 #define LPDDR2_TRFC_4GBIT (130) /* ns */ 386 #define LPDDR2_TDQSCK_MIN (2) /* tDQSCKmin, 2.5ns */ 387 #define LPDDR2_TDQSCK_MAX (5) /* tDQSCKmax, 5.5ns */ 388 389 /*pd and sr*/ 390 #define LPDDR2_TXP (7) /* tXP, max(2tCK,7.5ns) */ 391 #define LPDDR2_TXPDLL (0) 392 #define LPDDR2_TDLLK (0) /* tCK */ 393 #define LPDDR2_TCKE (3) /* tCK */ 394 #define LPDDR2_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 395 #define LPDDR2_TCKSRE (1) /* tCK */ 396 #define LPDDR2_TCKSRX (2) /* tCK */ 397 398 /*mode register timing*/ 399 #define LPDDR2_TMOD (0) 400 #define LPDDR2_TMRD (5) /* tMRD, (=tMRW), 5 tCK */ 401 #define LPDDR2_TMRR (2) /* tCK */ 402 403 /*ZQ*/ 404 #define LPDDR2_TZQINIT (1000) /* ns */ 405 #define LPDDR2_TZQCS (90) /* tZQCS, max(6tCK,90ns) */ 406 #define LPDDR2_TZQCL (360) /* tZQCL, max(6tCK,360ns) */ 407 #define LPDDR2_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 408 409 /* 410 * Description: depend on input parameter "timing_config", 411 * and calculate all lpddr2 412 * spec timing to "pdram_timing" 413 * parameters: 414 * input: timing_config 415 * output: pdram_timing 416 */ 417 static void lpddr2_get_parameter(struct timing_related_config *timing_config, 418 struct dram_timing_t *pdram_timing) 419 { 420 uint32_t nmhz = timing_config->freq; 421 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 422 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 423 424 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 425 pdram_timing->mhz = nmhz; 426 pdram_timing->al = 0; 427 pdram_timing->bl = timing_config->bl; 428 429 /* 1066 933 800 667 533 400 333 430 * RL, 8 7 6 5 4 3 3 431 * WL, 4 4 3 2 2 1 1 432 */ 433 if (nmhz <= 266) { 434 pdram_timing->cl = 4; 435 pdram_timing->cwl = 2; 436 pdram_timing->mr[2] = LPDDR2_RL4_WL2; 437 } else if (nmhz <= 333) { 438 pdram_timing->cl = 5; 439 pdram_timing->cwl = 2; 440 pdram_timing->mr[2] = LPDDR2_RL5_WL2; 441 } else if (nmhz <= 400) { 442 pdram_timing->cl = 6; 443 pdram_timing->cwl = 3; 444 pdram_timing->mr[2] = LPDDR2_RL6_WL3; 445 } else if (nmhz <= 466) { 446 pdram_timing->cl = 7; 447 pdram_timing->cwl = 4; 448 pdram_timing->mr[2] = LPDDR2_RL7_WL4; 449 } else { 450 pdram_timing->cl = 8; 451 pdram_timing->cwl = 4; 452 pdram_timing->mr[2] = LPDDR2_RL8_WL4; 453 } 454 switch (timing_config->dramds) { 455 case 120: 456 pdram_timing->mr[3] = LPDDR2_DS_120; 457 break; 458 case 80: 459 pdram_timing->mr[3] = LPDDR2_DS_80; 460 break; 461 case 60: 462 pdram_timing->mr[3] = LPDDR2_DS_60; 463 break; 464 case 48: 465 pdram_timing->mr[3] = LPDDR2_DS_48; 466 break; 467 case 40: 468 pdram_timing->mr[3] = LPDDR2_DS_40; 469 break; 470 case 34: 471 default: 472 pdram_timing->mr[3] = LPDDR2_DS_34; 473 break; 474 } 475 pdram_timing->mr[0] = 0; 476 477 pdram_timing->tinit1 = (LPDDR2_TINIT1 * nmhz + 999) / 1000; 478 pdram_timing->tinit2 = LPDDR2_TINIT2; 479 pdram_timing->tinit3 = (LPDDR2_TINIT3 * nmhz + 999) / 1000; 480 pdram_timing->tinit4 = (LPDDR2_TINIT4 * nmhz + 999) / 1000; 481 pdram_timing->tinit5 = (LPDDR2_TINIT5 * nmhz + 999) / 1000; 482 pdram_timing->trstl = LPDDR2_TRSTL; 483 pdram_timing->trsth = (LPDDR2_TRSTH * nmhz + 999) / 1000; 484 /* 485 * tREFI, average periodic refresh interval, 486 * 15.6us(<256Mb) 7.8us(256Mb-1Gb) 3.9us(2Gb-8Gb) 487 */ 488 if (ddr_capability_per_die >= 0x10000000) 489 pdram_timing->trefi = (LPDDR2_TREFI_3_9_US * nmhz + 999) 490 / 1000; 491 else 492 pdram_timing->trefi = (LPDDR2_TREFI_7_8_US * nmhz + 999) 493 / 1000; 494 /* base timing */ 495 tmp = ((LPDDR2_TRCD * nmhz + 999) / 1000); 496 pdram_timing->trcd = max(3, tmp); 497 /* 498 * tRPpb, max(3tCK, 15ns(Fast) 18ns(Typ) 24ns(Slow), 499 */ 500 trppb_tmp = ((LPDDR2_TRP_PB * nmhz + 999) / 1000); 501 trppb_tmp = max(3, trppb_tmp); 502 pdram_timing->trppb = trppb_tmp; 503 /* 504 * tRPab, max(3tCK, 4-bank:15ns(Fast) 18ns(Typ) 24ns(Slow), 505 * 8-bank:18ns(Fast) 21ns(Typ) 27ns(Slow)) 506 */ 507 trp_tmp = ((LPDDR2_TRP_AB_8_BANK * nmhz + 999) / 1000); 508 trp_tmp = max(3, trp_tmp); 509 pdram_timing->trp = trp_tmp; 510 twr_tmp = ((LPDDR2_TWR * nmhz + 999) / 1000); 511 twr_tmp = max(3, twr_tmp); 512 pdram_timing->twr = twr_tmp; 513 bl_tmp = (pdram_timing->bl == 16) ? LPDDR2_BL16 : 514 ((pdram_timing->bl == 8) ? LPDDR2_BL8 : LPDDR2_BL4); 515 pdram_timing->mr[1] = bl_tmp | LPDDR2_N_WR(twr_tmp); 516 tmp = ((LPDDR2_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 517 pdram_timing->trtp = max(2, tmp); 518 tras_tmp = ((LPDDR2_TRAS * nmhz + 999) / 1000); 519 tras_tmp = max(3, tras_tmp); 520 pdram_timing->tras_min = tras_tmp; 521 pdram_timing->tras_max = ((LPDDR2_TRAS_MAX * nmhz + 999) / 1000); 522 pdram_timing->trc = (tras_tmp + trp_tmp); 523 tmp = ((LPDDR2_TRRD * nmhz + 999) / 1000); 524 pdram_timing->trrd = max(2, tmp); 525 pdram_timing->tccd = LPDDR2_TCCD; 526 /* tWTR, max(2tCK, 7.5ns(533-266MHz) 10ns(200-166MHz)) */ 527 if (nmhz > 200) 528 tmp = ((LPDDR2_TWTR_GREAT_200MHZ * nmhz + (nmhz >> 1) + 529 999) / 1000); 530 else 531 tmp = ((LPDDR2_TWTR_LITTLE_200MHZ * nmhz + 999) / 1000); 532 pdram_timing->twtr = max(2, tmp); 533 pdram_timing->trtw = LPDDR2_TRTW; 534 if (nmhz <= 200) 535 pdram_timing->tfaw = (LPDDR2_TFAW_LITTLE_200MHZ * nmhz + 999) 536 / 1000; 537 else 538 pdram_timing->tfaw = (LPDDR2_TFAW_GREAT_200MHZ * nmhz + 999) 539 / 1000; 540 /* tRFC, 90ns(<=512Mb) 130ns(1Gb-4Gb) 210ns(8Gb) */ 541 if (ddr_capability_per_die >= 0x40000000) { 542 pdram_timing->trfc = 543 (LPDDR2_TRFC_8GBIT * nmhz + 999) / 1000; 544 tmp = (((LPDDR2_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 545 } else { 546 pdram_timing->trfc = 547 (LPDDR2_TRFC_4GBIT * nmhz + 999) / 1000; 548 tmp = (((LPDDR2_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 549 } 550 if (tmp < 2) 551 tmp = 2; 552 pdram_timing->txsr = tmp; 553 pdram_timing->txsnr = tmp; 554 /* tdqsck use rounded down */ 555 pdram_timing->tdqsck = ((LPDDR2_TDQSCK_MIN * nmhz + (nmhz >> 1)) 556 / 1000); 557 pdram_timing->tdqsck_max = 558 ((LPDDR2_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 559 / 1000); 560 /* pd and sr */ 561 tmp = ((LPDDR2_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 562 pdram_timing->txp = max(2, tmp); 563 pdram_timing->txpdll = LPDDR2_TXPDLL; 564 pdram_timing->tdllk = LPDDR2_TDLLK; 565 pdram_timing->tcke = LPDDR2_TCKE; 566 tmp = ((LPDDR2_TCKESR * nmhz + 999) / 1000); 567 pdram_timing->tckesr = max(3, tmp); 568 pdram_timing->tcksre = LPDDR2_TCKSRE; 569 pdram_timing->tcksrx = LPDDR2_TCKSRX; 570 /* mode register timing */ 571 pdram_timing->tmod = LPDDR2_TMOD; 572 pdram_timing->tmrd = LPDDR2_TMRD; 573 pdram_timing->tmrr = LPDDR2_TMRR; 574 /* ZQ */ 575 pdram_timing->tzqinit = (LPDDR2_TZQINIT * nmhz + 999) / 1000; 576 tmp = ((LPDDR2_TZQCS * nmhz + 999) / 1000); 577 pdram_timing->tzqcs = max(6, tmp); 578 tmp = ((LPDDR2_TZQCL * nmhz + 999) / 1000); 579 pdram_timing->tzqoper = max(6, tmp); 580 tmp = ((LPDDR2_TZQRESET * nmhz + 999) / 1000); 581 pdram_timing->tzqreset = max(3, tmp); 582 } 583 584 #define LPDDR3_TINIT1 (100) /* ns */ 585 #define LPDDR3_TINIT2 (5) /* tCK */ 586 #define LPDDR3_TINIT3 (200000) /* 200us */ 587 #define LPDDR3_TINIT4 (1000) /* 1us */ 588 #define LPDDR3_TINIT5 (10000) /* 10us */ 589 #define LPDDR3_TRSTL (0) 590 #define LPDDR3_TRSTH (0) /* 500us */ 591 #define LPDDR3_TREFI_3_9_US (3900) /* 3.9us */ 592 593 /* base timging */ 594 #define LPDDR3_TRCD (18) /* tRCD,15ns(Fast)18ns(Typ)24ns(Slow) */ 595 #define LPDDR3_TRP_PB (18) /* tRPpb, 15ns(Fast) 18ns(Typ) 24ns(Slow) */ 596 #define LPDDR3_TRP_AB (21) /* tRPab, 18ns(Fast) 21ns(Typ) 27ns(Slow) */ 597 #define LPDDR3_TWR (15) /* tWR, max(4tCK,15ns) */ 598 #define LPDDR3_TRTP (7) /* tRTP, max(4tCK, 7.5ns) */ 599 #define LPDDR3_TRRD (10) /* tRRD, max(2tCK,10ns) */ 600 #define LPDDR3_TCCD (4) /* tCK */ 601 #define LPDDR3_TWTR (7) /* tWTR, max(4tCK, 7.5ns) */ 602 #define LPDDR3_TRTW (0) /* tCK register min valid value */ 603 #define LPDDR3_TRAS_MAX (70000) /* 70us */ 604 #define LPDDR3_TRAS (42) /* tRAS, max(3tCK,42ns) */ 605 #define LPDDR3_TFAW (50) /* tFAW,max(8tCK, 50ns) */ 606 #define LPDDR3_TRFC_8GBIT (210) /* tRFC, 130ns(4Gb) 210ns(>4Gb) */ 607 #define LPDDR3_TRFC_4GBIT (130) /* ns */ 608 #define LPDDR3_TDQSCK_MIN (2) /* tDQSCKmin,2.5ns */ 609 #define LPDDR3_TDQSCK_MAX (5) /* tDQSCKmax,5.5ns */ 610 611 /* pd and sr */ 612 #define LPDDR3_TXP (7) /* tXP, max(3tCK,7.5ns) */ 613 #define LPDDR3_TXPDLL (0) 614 #define LPDDR3_TCKE (7) /* tCKE, (max 7.5ns,3 tCK) */ 615 #define LPDDR3_TCKESR (15) /* tCKESR, max(3tCK,15ns) */ 616 #define LPDDR3_TCKSRE (2) /* tCKSRE=tCPDED, 2 tCK */ 617 #define LPDDR3_TCKSRX (2) /* tCKSRX, 2 tCK */ 618 619 /* mode register timing */ 620 #define LPDDR3_TMOD (0) 621 #define LPDDR3_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 622 #define LPDDR3_TMRR (4) /* tMRR, 4 tCK */ 623 #define LPDDR3_TMRRI LPDDR3_TRCD 624 625 /* ODT */ 626 #define LPDDR3_TODTON (3) /* 3.5ns */ 627 628 /* ZQ */ 629 #define LPDDR3_TZQINIT (1000) /* 1us */ 630 #define LPDDR3_TZQCS (90) /* tZQCS, 90ns */ 631 #define LPDDR3_TZQCL (360) /* 360ns */ 632 #define LPDDR3_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 633 /* write leveling */ 634 #define LPDDR3_TWLMRD (40) /* ns */ 635 #define LPDDR3_TWLO (20) /* ns */ 636 #define LPDDR3_TWLDQSEN (25) /* ns */ 637 /* CA training */ 638 #define LPDDR3_TCACKEL (10) /* tCK */ 639 #define LPDDR3_TCAENT (10) /* tCK */ 640 #define LPDDR3_TCAMRD (20) /* tCK */ 641 #define LPDDR3_TCACKEH (10) /* tCK */ 642 #define LPDDR3_TCAEXT (10) /* tCK */ 643 #define LPDDR3_TADR (20) /* ns */ 644 #define LPDDR3_TMRZ (3) /* ns */ 645 646 /* FSP */ 647 #define LPDDR3_TFC_LONG (250) /* ns */ 648 649 /* 650 * Description: depend on input parameter "timing_config", 651 * and calculate all lpddr3 652 * spec timing to "pdram_timing" 653 * parameters: 654 * input: timing_config 655 * output: pdram_timing 656 */ 657 static void lpddr3_get_parameter(struct timing_related_config *timing_config, 658 struct dram_timing_t *pdram_timing) 659 { 660 uint32_t nmhz = timing_config->freq; 661 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 662 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp, twr_tmp, bl_tmp; 663 664 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 665 pdram_timing->mhz = nmhz; 666 pdram_timing->al = 0; 667 pdram_timing->bl = timing_config->bl; 668 669 /* 670 * Only support Write Latency Set A here 671 * 1066 933 800 733 667 600 533 400 166 672 * RL, 16 14 12 11 10 9 8 6 3 673 * WL, 8 8 6 6 6 5 4 3 1 674 */ 675 if (nmhz <= 400) { 676 pdram_timing->cl = 6; 677 pdram_timing->cwl = 3; 678 pdram_timing->mr[2] = LPDDR3_RL6_WL3; 679 } else if (nmhz <= 533) { 680 pdram_timing->cl = 8; 681 pdram_timing->cwl = 4; 682 pdram_timing->mr[2] = LPDDR3_RL8_WL4; 683 } else if (nmhz <= 600) { 684 pdram_timing->cl = 9; 685 pdram_timing->cwl = 5; 686 pdram_timing->mr[2] = LPDDR3_RL9_WL5; 687 } else if (nmhz <= 667) { 688 pdram_timing->cl = 10; 689 pdram_timing->cwl = 6; 690 pdram_timing->mr[2] = LPDDR3_RL10_WL6; 691 } else if (nmhz <= 733) { 692 pdram_timing->cl = 11; 693 pdram_timing->cwl = 6; 694 pdram_timing->mr[2] = LPDDR3_RL11_WL6; 695 } else if (nmhz <= 800) { 696 pdram_timing->cl = 12; 697 pdram_timing->cwl = 6; 698 pdram_timing->mr[2] = LPDDR3_RL12_WL6; 699 } else if (nmhz <= 933) { 700 pdram_timing->cl = 14; 701 pdram_timing->cwl = 8; 702 pdram_timing->mr[2] = LPDDR3_RL14_WL8; 703 } else { 704 pdram_timing->cl = 16; 705 pdram_timing->cwl = 8; 706 pdram_timing->mr[2] = LPDDR3_RL16_WL8; 707 } 708 switch (timing_config->dramds) { 709 case 80: 710 pdram_timing->mr[3] = LPDDR3_DS_80; 711 break; 712 case 60: 713 pdram_timing->mr[3] = LPDDR3_DS_60; 714 break; 715 case 48: 716 pdram_timing->mr[3] = LPDDR3_DS_48; 717 break; 718 case 40: 719 pdram_timing->mr[3] = LPDDR3_DS_40; 720 break; 721 case 3440: 722 pdram_timing->mr[3] = LPDDR3_DS_34D_40U; 723 break; 724 case 4048: 725 pdram_timing->mr[3] = LPDDR3_DS_40D_48U; 726 break; 727 case 3448: 728 pdram_timing->mr[3] = LPDDR3_DS_34D_48U; 729 break; 730 case 34: 731 default: 732 pdram_timing->mr[3] = LPDDR3_DS_34; 733 break; 734 } 735 pdram_timing->mr[0] = 0; 736 if (timing_config->odt) 737 switch (timing_config->dramodt) { 738 case 60: 739 pdram_timing->mr11 = LPDDR3_ODT_60; 740 break; 741 case 120: 742 pdram_timing->mr11 = LPDDR3_ODT_120; 743 break; 744 case 240: 745 default: 746 pdram_timing->mr11 = LPDDR3_ODT_240; 747 break; 748 } 749 else 750 pdram_timing->mr11 = LPDDR3_ODT_DIS; 751 752 pdram_timing->tinit1 = (LPDDR3_TINIT1 * nmhz + 999) / 1000; 753 pdram_timing->tinit2 = LPDDR3_TINIT2; 754 pdram_timing->tinit3 = (LPDDR3_TINIT3 * nmhz + 999) / 1000; 755 pdram_timing->tinit4 = (LPDDR3_TINIT4 * nmhz + 999) / 1000; 756 pdram_timing->tinit5 = (LPDDR3_TINIT5 * nmhz + 999) / 1000; 757 pdram_timing->trstl = LPDDR3_TRSTL; 758 pdram_timing->trsth = (LPDDR3_TRSTH * nmhz + 999) / 1000; 759 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 760 pdram_timing->trefi = (LPDDR3_TREFI_3_9_US * nmhz + 999) / 1000; 761 /* base timing */ 762 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 763 pdram_timing->trcd = max(3, tmp); 764 trppb_tmp = ((LPDDR3_TRP_PB * nmhz + 999) / 1000); 765 trppb_tmp = max(3, trppb_tmp); 766 pdram_timing->trppb = trppb_tmp; 767 trp_tmp = ((LPDDR3_TRP_AB * nmhz + 999) / 1000); 768 trp_tmp = max(3, trp_tmp); 769 pdram_timing->trp = trp_tmp; 770 twr_tmp = ((LPDDR3_TWR * nmhz + 999) / 1000); 771 twr_tmp = max(4, twr_tmp); 772 pdram_timing->twr = twr_tmp; 773 if (twr_tmp <= 6) 774 twr_tmp = 6; 775 else if (twr_tmp <= 8) 776 twr_tmp = 8; 777 else if (twr_tmp <= 12) 778 twr_tmp = twr_tmp; 779 else if (twr_tmp <= 14) 780 twr_tmp = 14; 781 else 782 twr_tmp = 16; 783 if (twr_tmp > 9) 784 pdram_timing->mr[2] |= (1 << 4); /*enable nWR > 9*/ 785 twr_tmp = (twr_tmp > 9) ? (twr_tmp - 10) : (twr_tmp - 2); 786 bl_tmp = LPDDR3_BL8; 787 pdram_timing->mr[1] = bl_tmp | LPDDR3_N_WR(twr_tmp); 788 tmp = ((LPDDR3_TRTP * nmhz + (nmhz >> 1) + 999) / 1000); 789 pdram_timing->trtp = max(4, tmp); 790 tras_tmp = ((LPDDR3_TRAS * nmhz + 999) / 1000); 791 tras_tmp = max(3, tras_tmp); 792 pdram_timing->tras_min = tras_tmp; 793 pdram_timing->trc = (tras_tmp + trp_tmp); 794 tmp = ((LPDDR3_TRRD * nmhz + 999) / 1000); 795 pdram_timing->trrd = max(2, tmp); 796 pdram_timing->tccd = LPDDR3_TCCD; 797 tmp = ((LPDDR3_TWTR * nmhz + (nmhz >> 1) + 999) / 1000); 798 pdram_timing->twtr = max(4, tmp); 799 pdram_timing->trtw = ((LPDDR3_TRTW * nmhz + 999) / 1000); 800 pdram_timing->tras_max = ((LPDDR3_TRAS_MAX * nmhz + 999) / 1000); 801 tmp = (LPDDR3_TFAW * nmhz + 999) / 1000; 802 pdram_timing->tfaw = max(8, tmp); 803 if (ddr_capability_per_die > 0x20000000) { 804 pdram_timing->trfc = 805 (LPDDR3_TRFC_8GBIT * nmhz + 999) / 1000; 806 tmp = (((LPDDR3_TRFC_8GBIT + 10) * nmhz + 999) / 1000); 807 } else { 808 pdram_timing->trfc = 809 (LPDDR3_TRFC_4GBIT * nmhz + 999) / 1000; 810 tmp = (((LPDDR3_TRFC_4GBIT + 10) * nmhz + 999) / 1000); 811 } 812 pdram_timing->txsr = max(2, tmp); 813 pdram_timing->txsnr = max(2, tmp); 814 /* tdqsck use rounded down */ 815 pdram_timing->tdqsck = 816 ((LPDDR3_TDQSCK_MIN * nmhz + (nmhz >> 1)) 817 / 1000); 818 pdram_timing->tdqsck_max = 819 ((LPDDR3_TDQSCK_MAX * nmhz + (nmhz >> 1) + 999) 820 / 1000); 821 /*pd and sr*/ 822 tmp = ((LPDDR3_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 823 pdram_timing->txp = max(3, tmp); 824 pdram_timing->txpdll = LPDDR3_TXPDLL; 825 tmp = ((LPDDR3_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 826 pdram_timing->tcke = max(3, tmp); 827 tmp = ((LPDDR3_TCKESR * nmhz + 999) / 1000); 828 pdram_timing->tckesr = max(3, tmp); 829 pdram_timing->tcksre = LPDDR3_TCKSRE; 830 pdram_timing->tcksrx = LPDDR3_TCKSRX; 831 /*mode register timing*/ 832 pdram_timing->tmod = LPDDR3_TMOD; 833 tmp = ((LPDDR3_TMRD * nmhz + 999) / 1000); 834 pdram_timing->tmrd = max(10, tmp); 835 pdram_timing->tmrr = LPDDR3_TMRR; 836 tmp = ((LPDDR3_TRCD * nmhz + 999) / 1000); 837 pdram_timing->tmrri = max(3, tmp); 838 /* ODT */ 839 pdram_timing->todton = (LPDDR3_TODTON * nmhz + (nmhz >> 1) + 999) 840 / 1000; 841 /* ZQ */ 842 pdram_timing->tzqinit = (LPDDR3_TZQINIT * nmhz + 999) / 1000; 843 pdram_timing->tzqcs = 844 ((LPDDR3_TZQCS * nmhz + 999) / 1000); 845 pdram_timing->tzqoper = 846 ((LPDDR3_TZQCL * nmhz + 999) / 1000); 847 tmp = ((LPDDR3_TZQRESET * nmhz + 999) / 1000); 848 pdram_timing->tzqreset = max(3, tmp); 849 /* write leveling */ 850 pdram_timing->twlmrd = (LPDDR3_TWLMRD * nmhz + 999) / 1000; 851 pdram_timing->twlo = (LPDDR3_TWLO * nmhz + 999) / 1000; 852 pdram_timing->twldqsen = (LPDDR3_TWLDQSEN * nmhz + 999) / 1000; 853 /* CA training */ 854 pdram_timing->tcackel = LPDDR3_TCACKEL; 855 pdram_timing->tcaent = LPDDR3_TCAENT; 856 pdram_timing->tcamrd = LPDDR3_TCAMRD; 857 pdram_timing->tcackeh = LPDDR3_TCACKEH; 858 pdram_timing->tcaext = LPDDR3_TCAEXT; 859 pdram_timing->tadr = (LPDDR3_TADR * nmhz + 999) / 1000; 860 pdram_timing->tmrz = (LPDDR3_TMRZ * nmhz + 999) / 1000; 861 pdram_timing->tcacd = pdram_timing->tadr + 2; 862 863 /* FSP */ 864 pdram_timing->tfc_long = (LPDDR3_TFC_LONG * nmhz + 999) / 1000; 865 } 866 867 #define LPDDR4_TINIT1 (200000) /* 200us */ 868 #define LPDDR4_TINIT2 (10) /* 10ns */ 869 #define LPDDR4_TINIT3 (2000000) /* 2ms */ 870 #define LPDDR4_TINIT4 (5) /* tCK */ 871 #define LPDDR4_TINIT5 (2000) /* 2us */ 872 #define LPDDR4_TRSTL LPDDR4_TINIT1 873 #define LPDDR4_TRSTH LPDDR4_TINIT3 874 #define LPDDR4_TREFI_3_9_US (3900) /* 3.9us */ 875 876 /* base timging */ 877 #define LPDDR4_TRCD (18) /* tRCD, max(18ns,4tCK) */ 878 #define LPDDR4_TRP_PB (18) /* tRPpb, max(18ns, 4tCK) */ 879 #define LPDDR4_TRP_AB (21) /* tRPab, max(21ns, 4tCK) */ 880 #define LPDDR4_TRRD (10) /* tRRD, max(4tCK,10ns) */ 881 #define LPDDR4_TCCD_BL16 (8) /* tCK */ 882 #define LPDDR4_TCCD_BL32 (16) /* tCK */ 883 #define LPDDR4_TWTR (10) /* tWTR, max(8tCK, 10ns) */ 884 #define LPDDR4_TRTW (0) /* tCK register min valid value */ 885 #define LPDDR4_TRAS_MAX (70000) /* 70us */ 886 #define LPDDR4_TRAS (42) /* tRAS, max(3tCK,42ns) */ 887 #define LPDDR4_TFAW (40) /* tFAW,min 40ns) */ 888 #define LPDDR4_TRFC_12GBIT (280) /* tRFC, 280ns(>=12Gb) */ 889 #define LPDDR4_TRFC_6GBIT (180) /* 6Gb/8Gb 180ns */ 890 #define LPDDR4_TRFC_4GBIT (130) /* 4Gb 130ns */ 891 #define LPDDR4_TDQSCK_MIN (1) /* tDQSCKmin,1.5ns */ 892 #define LPDDR4_TDQSCK_MAX (3) /* tDQSCKmax,3.5ns */ 893 #define LPDDR4_TPPD (4) /* tCK */ 894 895 /* pd and sr */ 896 #define LPDDR4_TXP (7) /* tXP, max(5tCK,7.5ns) */ 897 #define LPDDR4_TCKE (7) /* tCKE, max(7.5ns,4 tCK) */ 898 #define LPDDR4_TESCKE (1) /* tESCKE, max(1.75ns, 3tCK) */ 899 #define LPDDR4_TSR (15) /* tSR, max(15ns, 3tCK) */ 900 #define LPDDR4_TCMDCKE (1) /* max(1.75ns, 3tCK) */ 901 #define LPDDR4_TCSCKE (1) /* 1.75ns */ 902 #define LPDDR4_TCKELCS (5) /* max(5ns, 5tCK) */ 903 #define LPDDR4_TCSCKEH (1) /* 1.75ns */ 904 #define LPDDR4_TCKEHCS (7) /* max(7.5ns, 5tCK) */ 905 #define LPDDR4_TMRWCKEL (14) /* max(14ns, 10tCK) */ 906 #define LPDDR4_TCKELCMD (7) /* max(7.5ns, 3tCK) */ 907 #define LPDDR4_TCKEHCMD (7) /* max(7.5ns, 3tCK) */ 908 #define LPDDR4_TCKELPD (7) /* max(7.5ns, 3tCK) */ 909 #define LPDDR4_TCKCKEL (7) /* max(7.5ns, 3tCK) */ 910 911 /* mode register timing */ 912 #define LPDDR4_TMRD (14) /* tMRD, (=tMRW), max(14ns, 10 tCK) */ 913 #define LPDDR4_TMRR (8) /* tMRR, 8 tCK */ 914 915 /* ODT */ 916 #define LPDDR4_TODTON (3) /* 3.5ns */ 917 918 /* ZQ */ 919 #define LPDDR4_TZQCAL (1000) /* 1us */ 920 #define LPDDR4_TZQLAT (30) /* tZQLAT, max(30ns,8tCK) */ 921 #define LPDDR4_TZQRESET (50) /* ZQreset, max(3tCK,50ns) */ 922 #define LPDDR4_TZQCKE (1) /* tZQCKE, max(1.75ns, 3tCK) */ 923 924 /* write leveling */ 925 #define LPDDR4_TWLMRD (40) /* tCK */ 926 #define LPDDR4_TWLO (20) /* ns */ 927 #define LPDDR4_TWLDQSEN (20) /* tCK */ 928 929 /* CA training */ 930 #define LPDDR4_TCAENT (250) /* ns */ 931 #define LPDDR4_TADR (20) /* ns */ 932 #define LPDDR4_TMRZ (1) /* 1.5ns */ 933 #define LPDDR4_TVREF_LONG (250) /* ns */ 934 #define LPDDR4_TVREF_SHORT (100) /* ns */ 935 936 /* VRCG */ 937 #define LPDDR4_TVRCG_ENABLE (200) /* ns */ 938 #define LPDDR4_TVRCG_DISABLE (100) /* ns */ 939 940 /* FSP */ 941 #define LPDDR4_TFC_LONG (250) /* ns */ 942 #define LPDDR4_TCKFSPE (7) /* max(7.5ns, 4tCK) */ 943 #define LPDDR4_TCKFSPX (7) /* max(7.5ns, 4tCK) */ 944 945 /* 946 * Description: depend on input parameter "timing_config", 947 * and calculate all lpddr4 948 * spec timing to "pdram_timing" 949 * parameters: 950 * input: timing_config 951 * output: pdram_timing 952 */ 953 static void lpddr4_get_parameter(struct timing_related_config *timing_config, 954 struct dram_timing_t *pdram_timing) 955 { 956 uint32_t nmhz = timing_config->freq; 957 uint32_t ddr_capability_per_die = get_max_die_capability(timing_config); 958 uint32_t tmp, trp_tmp, trppb_tmp, tras_tmp; 959 960 zeromem((void *)pdram_timing, sizeof(struct dram_timing_t)); 961 pdram_timing->mhz = nmhz; 962 pdram_timing->al = 0; 963 pdram_timing->bl = timing_config->bl; 964 965 /* 966 * Only support Write Latency Set A here 967 * 2133 1866 1600 1333 1066 800 533 266 968 * RL, 36 32 28 24 20 14 10 6 969 * WL, 18 16 14 12 10 8 6 4 970 * nWR, 40 34 30 24 20 16 10 6 971 * nRTP,16 14 12 10 8 8 8 8 972 */ 973 tmp = (timing_config->bl == 32) ? 1 : 0; 974 975 /* 976 * we always use WR preamble = 2tCK 977 * RD preamble = Static 978 */ 979 tmp |= (1 << 2); 980 if (nmhz <= 266) { 981 pdram_timing->cl = 6; 982 pdram_timing->cwl = 4; 983 pdram_timing->twr = 6; 984 pdram_timing->trtp = 8; 985 pdram_timing->mr[2] = LPDDR4_RL6_NRTP8 | LPDDR4_A_WL4; 986 } else if (nmhz <= 533) { 987 if (timing_config->rdbi) { 988 pdram_timing->cl = 12; 989 pdram_timing->mr[2] = LPDDR4_RL12_NRTP8 | LPDDR4_A_WL6; 990 } else { 991 pdram_timing->cl = 10; 992 pdram_timing->mr[2] = LPDDR4_RL10_NRTP8 | LPDDR4_A_WL6; 993 } 994 pdram_timing->cwl = 6; 995 pdram_timing->twr = 10; 996 pdram_timing->trtp = 8; 997 tmp |= (1 << 4); 998 } else if (nmhz <= 800) { 999 if (timing_config->rdbi) { 1000 pdram_timing->cl = 16; 1001 pdram_timing->mr[2] = LPDDR4_RL16_NRTP8 | LPDDR4_A_WL8; 1002 } else { 1003 pdram_timing->cl = 14; 1004 pdram_timing->mr[2] = LPDDR4_RL14_NRTP8 | LPDDR4_A_WL8; 1005 } 1006 pdram_timing->cwl = 8; 1007 pdram_timing->twr = 16; 1008 pdram_timing->trtp = 8; 1009 tmp |= (2 << 4); 1010 } else if (nmhz <= 1066) { 1011 if (timing_config->rdbi) { 1012 pdram_timing->cl = 22; 1013 pdram_timing->mr[2] = LPDDR4_RL22_NRTP8 | LPDDR4_A_WL10; 1014 } else { 1015 pdram_timing->cl = 20; 1016 pdram_timing->mr[2] = LPDDR4_RL20_NRTP8 | LPDDR4_A_WL10; 1017 } 1018 pdram_timing->cwl = 10; 1019 pdram_timing->twr = 20; 1020 pdram_timing->trtp = 8; 1021 tmp |= (3 << 4); 1022 } else if (nmhz <= 1333) { 1023 if (timing_config->rdbi) { 1024 pdram_timing->cl = 28; 1025 pdram_timing->mr[2] = LPDDR4_RL28_NRTP10 | 1026 LPDDR4_A_WL12; 1027 } else { 1028 pdram_timing->cl = 24; 1029 pdram_timing->mr[2] = LPDDR4_RL24_NRTP10 | 1030 LPDDR4_A_WL12; 1031 } 1032 pdram_timing->cwl = 12; 1033 pdram_timing->twr = 24; 1034 pdram_timing->trtp = 10; 1035 tmp |= (4 << 4); 1036 } else if (nmhz <= 1600) { 1037 if (timing_config->rdbi) { 1038 pdram_timing->cl = 32; 1039 pdram_timing->mr[2] = LPDDR4_RL32_NRTP12 | 1040 LPDDR4_A_WL14; 1041 } else { 1042 pdram_timing->cl = 28; 1043 pdram_timing->mr[2] = LPDDR4_RL28_NRTP12 | 1044 LPDDR4_A_WL14; 1045 } 1046 pdram_timing->cwl = 14; 1047 pdram_timing->twr = 30; 1048 pdram_timing->trtp = 12; 1049 tmp |= (5 << 4); 1050 } else if (nmhz <= 1866) { 1051 if (timing_config->rdbi) { 1052 pdram_timing->cl = 36; 1053 pdram_timing->mr[2] = LPDDR4_RL36_NRTP14 | 1054 LPDDR4_A_WL16; 1055 } else { 1056 pdram_timing->cl = 32; 1057 pdram_timing->mr[2] = LPDDR4_RL32_NRTP14 | 1058 LPDDR4_A_WL16; 1059 } 1060 pdram_timing->cwl = 16; 1061 pdram_timing->twr = 34; 1062 pdram_timing->trtp = 14; 1063 tmp |= (6 << 4); 1064 } else { 1065 if (timing_config->rdbi) { 1066 pdram_timing->cl = 40; 1067 pdram_timing->mr[2] = LPDDR4_RL40_NRTP16 | 1068 LPDDR4_A_WL18; 1069 } else { 1070 pdram_timing->cl = 36; 1071 pdram_timing->mr[2] = LPDDR4_RL36_NRTP16 | 1072 LPDDR4_A_WL18; 1073 } 1074 pdram_timing->cwl = 18; 1075 pdram_timing->twr = 40; 1076 pdram_timing->trtp = 16; 1077 tmp |= (7 << 4); 1078 } 1079 pdram_timing->mr[1] = tmp; 1080 tmp = (timing_config->rdbi ? LPDDR4_DBI_RD_EN : 0) | 1081 (timing_config->wdbi ? LPDDR4_DBI_WR_EN : 0); 1082 switch (timing_config->dramds) { 1083 case 240: 1084 pdram_timing->mr[3] = LPDDR4_PDDS_240 | tmp; 1085 break; 1086 case 120: 1087 pdram_timing->mr[3] = LPDDR4_PDDS_120 | tmp; 1088 break; 1089 case 80: 1090 pdram_timing->mr[3] = LPDDR4_PDDS_80 | tmp; 1091 break; 1092 case 60: 1093 pdram_timing->mr[3] = LPDDR4_PDDS_60 | tmp; 1094 break; 1095 case 48: 1096 pdram_timing->mr[3] = LPDDR4_PDDS_48 | tmp; 1097 break; 1098 case 40: 1099 default: 1100 pdram_timing->mr[3] = LPDDR4_PDDS_40 | tmp; 1101 break; 1102 } 1103 pdram_timing->mr[0] = 0; 1104 if (timing_config->odt) { 1105 switch (timing_config->dramodt) { 1106 case 240: 1107 tmp = LPDDR4_DQODT_240; 1108 break; 1109 case 120: 1110 tmp = LPDDR4_DQODT_120; 1111 break; 1112 case 80: 1113 tmp = LPDDR4_DQODT_80; 1114 break; 1115 case 60: 1116 tmp = LPDDR4_DQODT_60; 1117 break; 1118 case 48: 1119 tmp = LPDDR4_DQODT_48; 1120 break; 1121 case 40: 1122 default: 1123 tmp = LPDDR4_DQODT_40; 1124 break; 1125 } 1126 1127 switch (timing_config->caodt) { 1128 case 240: 1129 pdram_timing->mr11 = LPDDR4_CAODT_240 | tmp; 1130 break; 1131 case 120: 1132 pdram_timing->mr11 = LPDDR4_CAODT_120 | tmp; 1133 break; 1134 case 80: 1135 pdram_timing->mr11 = LPDDR4_CAODT_80 | tmp; 1136 break; 1137 case 60: 1138 pdram_timing->mr11 = LPDDR4_CAODT_60 | tmp; 1139 break; 1140 case 48: 1141 pdram_timing->mr11 = LPDDR4_CAODT_48 | tmp; 1142 break; 1143 case 40: 1144 default: 1145 pdram_timing->mr11 = LPDDR4_CAODT_40 | tmp; 1146 break; 1147 } 1148 } else { 1149 pdram_timing->mr11 = LPDDR4_CAODT_DIS | tmp; 1150 } 1151 1152 pdram_timing->tinit1 = (LPDDR4_TINIT1 * nmhz + 999) / 1000; 1153 pdram_timing->tinit2 = (LPDDR4_TINIT2 * nmhz + 999) / 1000; 1154 pdram_timing->tinit3 = (LPDDR4_TINIT3 * nmhz + 999) / 1000; 1155 pdram_timing->tinit4 = (LPDDR4_TINIT4 * nmhz + 999) / 1000; 1156 pdram_timing->tinit5 = (LPDDR4_TINIT5 * nmhz + 999) / 1000; 1157 pdram_timing->trstl = (LPDDR4_TRSTL * nmhz + 999) / 1000; 1158 pdram_timing->trsth = (LPDDR4_TRSTH * nmhz + 999) / 1000; 1159 /* tREFI, average periodic refresh interval, 3.9us(4Gb-16Gb) */ 1160 pdram_timing->trefi = (LPDDR4_TREFI_3_9_US * nmhz + 999) / 1000; 1161 /* base timing */ 1162 tmp = ((LPDDR4_TRCD * nmhz + 999) / 1000); 1163 pdram_timing->trcd = max(4, tmp); 1164 trppb_tmp = ((LPDDR4_TRP_PB * nmhz + 999) / 1000); 1165 trppb_tmp = max(4, trppb_tmp); 1166 pdram_timing->trppb = trppb_tmp; 1167 trp_tmp = ((LPDDR4_TRP_AB * nmhz + 999) / 1000); 1168 trp_tmp = max(4, trp_tmp); 1169 pdram_timing->trp = trp_tmp; 1170 tras_tmp = ((LPDDR4_TRAS * nmhz + 999) / 1000); 1171 tras_tmp = max(3, tras_tmp); 1172 pdram_timing->tras_min = tras_tmp; 1173 pdram_timing->trc = (tras_tmp + trp_tmp); 1174 tmp = ((LPDDR4_TRRD * nmhz + 999) / 1000); 1175 pdram_timing->trrd = max(4, tmp); 1176 if (timing_config->bl == 32) 1177 pdram_timing->tccd = LPDDR4_TCCD_BL16; 1178 else 1179 pdram_timing->tccd = LPDDR4_TCCD_BL32; 1180 pdram_timing->tccdmw = 4 * pdram_timing->tccd; 1181 tmp = ((LPDDR4_TWTR * nmhz + 999) / 1000); 1182 pdram_timing->twtr = max(8, tmp); 1183 pdram_timing->trtw = ((LPDDR4_TRTW * nmhz + 999) / 1000); 1184 pdram_timing->tras_max = ((LPDDR4_TRAS_MAX * nmhz + 999) / 1000); 1185 pdram_timing->tfaw = (LPDDR4_TFAW * nmhz + 999) / 1000; 1186 if (ddr_capability_per_die > 0x60000000) { 1187 /* >= 12Gb */ 1188 pdram_timing->trfc = 1189 (LPDDR4_TRFC_12GBIT * nmhz + 999) / 1000; 1190 tmp = (((LPDDR4_TRFC_12GBIT + 7) * nmhz + (nmhz >> 1) + 1191 999) / 1000); 1192 } else if (ddr_capability_per_die > 0x30000000) { 1193 pdram_timing->trfc = 1194 (LPDDR4_TRFC_6GBIT * nmhz + 999) / 1000; 1195 tmp = (((LPDDR4_TRFC_6GBIT + 7) * nmhz + (nmhz >> 1) + 1196 999) / 1000); 1197 } else { 1198 pdram_timing->trfc = 1199 (LPDDR4_TRFC_4GBIT * nmhz + 999) / 1000; 1200 tmp = (((LPDDR4_TRFC_4GBIT + 7) * nmhz + (nmhz >> 1) + 1201 999) / 1000); 1202 } 1203 pdram_timing->txsr = max(2, tmp); 1204 pdram_timing->txsnr = max(2, tmp); 1205 /* tdqsck use rounded down */ 1206 pdram_timing->tdqsck = ((LPDDR4_TDQSCK_MIN * nmhz + 1207 (nmhz >> 1)) / 1000); 1208 pdram_timing->tdqsck_max = ((LPDDR4_TDQSCK_MAX * nmhz + 1209 (nmhz >> 1) + 999) / 1000); 1210 pdram_timing->tppd = LPDDR4_TPPD; 1211 /* pd and sr */ 1212 tmp = ((LPDDR4_TXP * nmhz + (nmhz >> 1) + 999) / 1000); 1213 pdram_timing->txp = max(5, tmp); 1214 tmp = ((LPDDR4_TCKE * nmhz + (nmhz >> 1) + 999) / 1000); 1215 pdram_timing->tcke = max(4, tmp); 1216 tmp = ((LPDDR4_TESCKE * nmhz + 1217 ((nmhz * 3) / 4) + 1218 999) / 1000); 1219 pdram_timing->tescke = max(3, tmp); 1220 tmp = ((LPDDR4_TSR * nmhz + 999) / 1000); 1221 pdram_timing->tsr = max(3, tmp); 1222 tmp = ((LPDDR4_TCMDCKE * nmhz + 1223 ((nmhz * 3) / 4) + 1224 999) / 1000); 1225 pdram_timing->tcmdcke = max(3, tmp); 1226 pdram_timing->tcscke = ((LPDDR4_TCSCKE * nmhz + 1227 ((nmhz * 3) / 4) + 1228 999) / 1000); 1229 tmp = ((LPDDR4_TCKELCS * nmhz + 999) / 1000); 1230 pdram_timing->tckelcs = max(5, tmp); 1231 pdram_timing->tcsckeh = ((LPDDR4_TCSCKEH * nmhz + 1232 ((nmhz * 3) / 4) + 1233 999) / 1000); 1234 tmp = ((LPDDR4_TCKEHCS * nmhz + 1235 (nmhz >> 1) + 999) / 1000); 1236 pdram_timing->tckehcs = max(5, tmp); 1237 tmp = ((LPDDR4_TMRWCKEL * nmhz + 999) / 1000); 1238 pdram_timing->tmrwckel = max(10, tmp); 1239 tmp = ((LPDDR4_TCKELCMD * nmhz + (nmhz >> 1) + 1240 999) / 1000); 1241 pdram_timing->tckelcmd = max(3, tmp); 1242 tmp = ((LPDDR4_TCKEHCMD * nmhz + (nmhz >> 1) + 1243 999) / 1000); 1244 pdram_timing->tckehcmd = max(3, tmp); 1245 tmp = ((LPDDR4_TCKELPD * nmhz + (nmhz >> 1) + 1246 999) / 1000); 1247 pdram_timing->tckelpd = max(3, tmp); 1248 tmp = ((LPDDR4_TCKCKEL * nmhz + (nmhz >> 1) + 1249 999) / 1000); 1250 pdram_timing->tckckel = max(3, tmp); 1251 /* mode register timing */ 1252 tmp = ((LPDDR4_TMRD * nmhz + 999) / 1000); 1253 pdram_timing->tmrd = max(10, tmp); 1254 pdram_timing->tmrr = LPDDR4_TMRR; 1255 pdram_timing->tmrri = pdram_timing->trcd + 3; 1256 /* ODT */ 1257 pdram_timing->todton = (LPDDR4_TODTON * nmhz + (nmhz >> 1) + 999) 1258 / 1000; 1259 /* ZQ */ 1260 pdram_timing->tzqcal = (LPDDR4_TZQCAL * nmhz + 999) / 1000; 1261 tmp = ((LPDDR4_TZQLAT * nmhz + 999) / 1000); 1262 pdram_timing->tzqlat = max(8, tmp); 1263 tmp = ((LPDDR4_TZQRESET * nmhz + 999) / 1000); 1264 pdram_timing->tzqreset = max(3, tmp); 1265 tmp = ((LPDDR4_TZQCKE * nmhz + 1266 ((nmhz * 3) / 4) + 1267 999) / 1000); 1268 pdram_timing->tzqcke = max(3, tmp); 1269 /* write leveling */ 1270 pdram_timing->twlmrd = LPDDR4_TWLMRD; 1271 pdram_timing->twlo = (LPDDR4_TWLO * nmhz + 999) / 1000; 1272 pdram_timing->twldqsen = LPDDR4_TWLDQSEN; 1273 /* CA training */ 1274 pdram_timing->tcaent = (LPDDR4_TCAENT * nmhz + 999) / 1000; 1275 pdram_timing->tadr = (LPDDR4_TADR * nmhz + 999) / 1000; 1276 pdram_timing->tmrz = (LPDDR4_TMRZ * nmhz + (nmhz >> 1) + 999) / 1000; 1277 pdram_timing->tvref_long = (LPDDR4_TVREF_LONG * nmhz + 999) / 1000; 1278 pdram_timing->tvref_short = (LPDDR4_TVREF_SHORT * nmhz + 999) / 1000; 1279 /* VRCG */ 1280 pdram_timing->tvrcg_enable = (LPDDR4_TVRCG_ENABLE * nmhz + 1281 999) / 1000; 1282 pdram_timing->tvrcg_disable = (LPDDR4_TVRCG_DISABLE * nmhz + 1283 999) / 1000; 1284 /* FSP */ 1285 pdram_timing->tfc_long = (LPDDR4_TFC_LONG * nmhz + 999) / 1000; 1286 tmp = (LPDDR4_TCKFSPE * nmhz + (nmhz >> 1) + 999) / 1000; 1287 pdram_timing->tckfspe = max(4, tmp); 1288 tmp = (LPDDR4_TCKFSPX * nmhz + (nmhz >> 1) + 999) / 1000; 1289 pdram_timing->tckfspx = max(4, tmp); 1290 } 1291 1292 /* 1293 * Description: depend on input parameter "timing_config", 1294 * and calculate correspond "dram_type" 1295 * spec timing to "pdram_timing" 1296 * parameters: 1297 * input: timing_config 1298 * output: pdram_timing 1299 * NOTE: MR ODT is set, need to disable by controller 1300 */ 1301 void dram_get_parameter(struct timing_related_config *timing_config, 1302 struct dram_timing_t *pdram_timing) 1303 { 1304 switch (timing_config->dram_type) { 1305 case DDR3: 1306 ddr3_get_parameter(timing_config, pdram_timing); 1307 break; 1308 case LPDDR2: 1309 lpddr2_get_parameter(timing_config, pdram_timing); 1310 break; 1311 case LPDDR3: 1312 lpddr3_get_parameter(timing_config, pdram_timing); 1313 break; 1314 case LPDDR4: 1315 lpddr4_get_parameter(timing_config, pdram_timing); 1316 break; 1317 } 1318 } 1319