1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <cortex_a53.h> 11#include <cortex_a57.h> 12#include <cortex_a72.h> 13#include <cpu_macros.S> 14#include <v2m_def.h> 15#include "../juno_def.h" 16 17 18 .globl plat_reset_handler 19 .globl plat_arm_calc_core_pos 20 21#define JUNO_REVISION(rev) REV_JUNO_R##rev 22#define JUNO_HANDLER(rev) plat_reset_handler_juno_r##rev 23#define JUMP_TO_HANDLER_IF_JUNO_R(revision) \ 24 jump_to_handler JUNO_REVISION(revision), JUNO_HANDLER(revision) 25 26 /* -------------------------------------------------------------------- 27 * Helper macro to jump to the given handler if the board revision 28 * matches. 29 * Expects the Juno board revision in x0. 30 * -------------------------------------------------------------------- 31 */ 32 .macro jump_to_handler _revision, _handler 33 cmp r0, #\_revision 34 beq \_handler 35 .endm 36 37 /* -------------------------------------------------------------------- 38 * Platform reset handler for Juno R0. 39 * 40 * Juno R0 has the following topology: 41 * - Quad core Cortex-A53 processor cluster; 42 * - Dual core Cortex-A57 processor cluster. 43 * 44 * This handler does the following: 45 * - Implement workaround for defect id 831273 by enabling an event 46 * stream every 65536 cycles. 47 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 48 * - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 49 * -------------------------------------------------------------------- 50 */ 51func JUNO_HANDLER(0) 52 /* -------------------------------------------------------------------- 53 * Enable the event stream every 65536 cycles 54 * -------------------------------------------------------------------- 55 */ 56 mov r0, #(0xf << EVNTI_SHIFT) 57 orr r0, r0, #EVNTEN_BIT 58 stcopr r0, CNTKCTL 59 60 /* -------------------------------------------------------------------- 61 * Nothing else to do on Cortex-A53. 62 * -------------------------------------------------------------------- 63 */ 64 jump_if_cpu_midr CORTEX_A53_MIDR, 1f 65 66 /* -------------------------------------------------------------------- 67 * Cortex-A57 specific settings 68 * -------------------------------------------------------------------- 69 */ 70 mov r0, #((CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 71 (CORTEX_A57_L2_TAG_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_TAG_RAM_LATENCY_SHIFT)) 72 stcopr r0, CORTEX_A57_L2CTLR 731: 74 isb 75 bx lr 76endfunc JUNO_HANDLER(0) 77 78 /* -------------------------------------------------------------------- 79 * Platform reset handler for Juno R1. 80 * 81 * Juno R1 has the following topology: 82 * - Quad core Cortex-A53 processor cluster; 83 * - Dual core Cortex-A57 processor cluster. 84 * 85 * This handler does the following: 86 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A57 87 * 88 * Note that: 89 * - The default value for the L2 Tag RAM latency for Cortex-A57 is 90 * suitable. 91 * - Defect #831273 doesn't affect Juno R1. 92 * -------------------------------------------------------------------- 93 */ 94func JUNO_HANDLER(1) 95 /* -------------------------------------------------------------------- 96 * Nothing to do on Cortex-A53. 97 * -------------------------------------------------------------------- 98 */ 99 jump_if_cpu_midr CORTEX_A57_MIDR, A57 100 bx lr 101 102A57: 103 /* -------------------------------------------------------------------- 104 * Cortex-A57 specific settings 105 * -------------------------------------------------------------------- 106 */ 107 mov r0, #(CORTEX_A57_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A57_L2CTLR_DATA_RAM_LATENCY_SHIFT) 108 stcopr r0, CORTEX_A57_L2CTLR 109 isb 110 bx lr 111endfunc JUNO_HANDLER(1) 112 113 /* -------------------------------------------------------------------- 114 * Platform reset handler for Juno R2. 115 * 116 * Juno R2 has the following topology: 117 * - Quad core Cortex-A53 processor cluster; 118 * - Dual core Cortex-A72 processor cluster. 119 * 120 * This handler does the following: 121 * - Set the L2 Data RAM latency to 2 (i.e. 3 cycles) for Cortex-A72 122 * - Set the L2 Tag RAM latency to 1 (i.e. 2 cycles) for Cortex-A72 123 * 124 * Note that: 125 * - Defect #831273 doesn't affect Juno R2. 126 * -------------------------------------------------------------------- 127 */ 128func JUNO_HANDLER(2) 129 /* -------------------------------------------------------------------- 130 * Nothing to do on Cortex-A53. 131 * -------------------------------------------------------------------- 132 */ 133 jump_if_cpu_midr CORTEX_A72_MIDR, A72 134 bx lr 135 136A72: 137 /* -------------------------------------------------------------------- 138 * Cortex-A72 specific settings 139 * -------------------------------------------------------------------- 140 */ 141 mov r0, #((CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ 142 (CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES << CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT)) 143 stcopr r0, CORTEX_A72_L2CTLR 144 isb 145 bx lr 146endfunc JUNO_HANDLER(2) 147 148 /* -------------------------------------------------------------------- 149 * void plat_reset_handler(void); 150 * 151 * Determine the Juno board revision and call the appropriate reset 152 * handler. 153 * -------------------------------------------------------------------- 154 */ 155func plat_reset_handler 156 /* Read the V2M SYS_ID register */ 157 ldr r0, =(V2M_SYSREGS_BASE + V2M_SYS_ID) 158 ldr r1, [r0] 159 /* Extract board revision from the SYS_ID */ 160 ubfx r0, r1, #V2M_SYS_ID_REV_SHIFT, #4 161 162 JUMP_TO_HANDLER_IF_JUNO_R(0) 163 JUMP_TO_HANDLER_IF_JUNO_R(1) 164 JUMP_TO_HANDLER_IF_JUNO_R(2) 165 166 /* Board revision is not supported */ 167 no_ret plat_panic_handler 168 169endfunc plat_reset_handler 170 171 /* ----------------------------------------------------- 172 * unsigned int plat_arm_calc_core_pos(u_register_t mpidr) 173 * Helper function to calculate the core position. 174 * ----------------------------------------------------- 175 */ 176func plat_arm_calc_core_pos 177 b css_calc_core_pos_swap_cluster 178endfunc plat_arm_calc_core_pos 179