1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CSS_DEF_H 8 #define CSS_DEF_H 9 10 #include <arm_def.h> 11 #include <gic_common.h> 12 #include <interrupt_props.h> 13 #include <tzc400.h> 14 15 /************************************************************************* 16 * Definitions common to all ARM Compute SubSystems (CSS) 17 *************************************************************************/ 18 #define NSROM_BASE 0x1f000000 19 #define NSROM_SIZE 0x00001000 20 21 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 22 #define CSS_DEVICE_BASE 0x20000000 23 #define CSS_DEVICE_SIZE 0x0e000000 24 25 /* System Security Control Registers */ 26 #define SSC_REG_BASE 0x2a420000 27 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 28 29 /* System ID Registers Unit */ 30 #define SID_REG_BASE 0x2a4a0000 31 #define SID_SYSTEM_ID_OFFSET 0x40 32 #define SID_SYSTEM_CFG_OFFSET 0x70 33 34 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 35 #define CSS_NIC400_SLAVE_BOOTSECURE 8 36 37 /* Interrupt handling constants */ 38 #define CSS_IRQ_MHU 69 39 #define CSS_IRQ_GPU_SMMU_0 71 40 #define CSS_IRQ_TZC 80 41 #define CSS_IRQ_TZ_WDOG 86 42 #define CSS_IRQ_SEC_SYS_TIMER 91 43 44 /* MHU register offsets */ 45 #define MHU_CPU_INTR_S_SET_OFFSET 0x308 46 47 /* 48 * Define a list of Group 1 Secure interrupt properties as per GICv3 49 * terminology. On a GICv2 system or mode, the interrupts will be treated as 50 * Group 0 interrupts. 51 */ 52 #define CSS_G1S_IRQ_PROPS(grp) \ 53 INTR_PROP_DESC(CSS_IRQ_MHU, GIC_HIGHEST_SEC_PRIORITY, grp, \ 54 GIC_INTR_CFG_LEVEL), \ 55 INTR_PROP_DESC(CSS_IRQ_GPU_SMMU_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ 56 GIC_INTR_CFG_LEVEL), \ 57 INTR_PROP_DESC(CSS_IRQ_TZC, GIC_HIGHEST_SEC_PRIORITY, grp, \ 58 GIC_INTR_CFG_LEVEL), \ 59 INTR_PROP_DESC(CSS_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, grp, \ 60 GIC_INTR_CFG_LEVEL), \ 61 INTR_PROP_DESC(CSS_IRQ_SEC_SYS_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 62 GIC_INTR_CFG_LEVEL) 63 64 #if CSS_USE_SCMI_SDS_DRIVER 65 /* Memory region for shared data storage */ 66 #define PLAT_ARM_SDS_MEM_BASE ARM_SHARED_RAM_BASE 67 #define PLAT_ARM_SDS_MEM_SIZE_MAX 0xDC0 /* 3520 bytes */ 68 /* 69 * The SCMI Channel is placed right after the SDS region 70 */ 71 #define CSS_SCMI_PAYLOAD_BASE (PLAT_ARM_SDS_MEM_BASE + PLAT_ARM_SDS_MEM_SIZE_MAX) 72 #define CSS_SCMI_MHU_DB_REG_OFF MHU_CPU_INTR_S_SET_OFFSET 73 74 /* Trusted mailbox base address common to all CSS */ 75 /* If SDS is present, then mailbox is at top of SRAM */ 76 #define PLAT_ARM_TRUSTED_MAILBOX_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE - 0x8) 77 78 /* Number of retries for SCP_RAM_READY flag */ 79 #define CSS_SCP_READY_10US_RETRIES 1000000 /* Effective timeout of 10000 ms */ 80 81 #else 82 /* 83 * SCP <=> AP boot configuration 84 * 85 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 86 * the start of the Trusted SRAM. 87 * 88 * Note that the value stored at this address is only valid at boot time, before 89 * the SCP_BL2 image is transferred to SCP. 90 */ 91 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 92 93 /* Trusted mailbox base address common to all CSS */ 94 /* If SDS is not present, then the mailbox is at the bottom of SRAM */ 95 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 96 97 #endif /* CSS_USE_SCMI_SDS_DRIVER */ 98 99 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 100 CSS_DEVICE_BASE, \ 101 CSS_DEVICE_SIZE, \ 102 MT_DEVICE | MT_RW | MT_SECURE) 103 104 #define CSS_MAP_NSRAM MAP_REGION_FLAT( \ 105 NSRAM_BASE, \ 106 NSRAM_SIZE, \ 107 MT_DEVICE | MT_RW | MT_NS) 108 109 #if defined(IMAGE_BL2U) 110 #define CSS_MAP_SCP_BL2U MAP_REGION_FLAT( \ 111 SCP_BL2U_BASE, \ 112 SCP_BL2U_LIMIT \ 113 - SCP_BL2U_BASE,\ 114 MT_RW_DATA | MT_SECURE) 115 #endif 116 117 /* Platform ID address */ 118 #define SSC_VERSION_OFFSET 0x040 119 120 #define SSC_VERSION_CONFIG_SHIFT 28 121 #define SSC_VERSION_MAJOR_REV_SHIFT 24 122 #define SSC_VERSION_MINOR_REV_SHIFT 20 123 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 124 #define SSC_VERSION_PART_NUM_SHIFT 0x0 125 #define SSC_VERSION_CONFIG_MASK 0xf 126 #define SSC_VERSION_MAJOR_REV_MASK 0xf 127 #define SSC_VERSION_MINOR_REV_MASK 0xf 128 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 129 #define SSC_VERSION_PART_NUM_MASK 0xfff 130 131 #define SID_SYSTEM_ID_PART_NUM_MASK 0xfff 132 133 /* SSC debug configuration registers */ 134 #define SSC_DBGCFG_SET 0x14 135 #define SSC_DBGCFG_CLR 0x18 136 137 #define SPIDEN_INT_CLR_SHIFT 6 138 #define SPIDEN_SEL_SET_SHIFT 7 139 140 #ifndef __ASSEMBLY__ 141 142 /* SSC_VERSION related accessors */ 143 144 /* Returns the part number of the platform */ 145 #define GET_SSC_VERSION_PART_NUM(val) \ 146 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 147 SSC_VERSION_PART_NUM_MASK) 148 149 /* Returns the configuration number of the platform */ 150 #define GET_SSC_VERSION_CONFIG(val) \ 151 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 152 SSC_VERSION_CONFIG_MASK) 153 154 #endif /* __ASSEMBLY__ */ 155 156 /************************************************************************* 157 * Required platform porting definitions common to all 158 * ARM Compute SubSystems (CSS) 159 ************************************************************************/ 160 161 /* 162 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 163 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 164 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 165 * an SCP_BL2/SCP_BL2U image. 166 */ 167 #if CSS_LOAD_SCP_IMAGES 168 169 #if ARM_BL31_IN_DRAM 170 #error "SCP_BL2 is not expected to be loaded by BL2 for ARM_BL31_IN_DRAM config" 171 #endif 172 173 /* 174 * Load address of SCP_BL2 in CSS platform ports 175 * SCP_BL2 is loaded to the same place as BL31 but it shouldn't overwrite BL1 176 * rw data or BL2. Once SCP_BL2 is transferred to the SCP, it is discarded and 177 * BL31 is loaded over the top. 178 */ 179 #define SCP_BL2_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2_SIZE) 180 #define SCP_BL2_LIMIT BL2_BASE 181 182 #define SCP_BL2U_BASE (BL2_BASE - PLAT_CSS_MAX_SCP_BL2U_SIZE) 183 #define SCP_BL2U_LIMIT BL2_BASE 184 #endif /* CSS_LOAD_SCP_IMAGES */ 185 186 /* Load address of Non-Secure Image for CSS platform ports */ 187 #define PLAT_ARM_NS_IMAGE_OFFSET U(0xE0000000) 188 189 /* TZC related constants */ 190 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 191 192 /* 193 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 194 * command 195 */ 196 #define CSS_CLUSTER_PWR_STATE_ON 0 197 #define CSS_CLUSTER_PWR_STATE_OFF 3 198 199 #define CSS_CPU_PWR_STATE_ON 1 200 #define CSS_CPU_PWR_STATE_OFF 0 201 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 202 203 #endif /* CSS_DEF_H */ 204