1 /* 2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 #include <assert.h> 7 #include <gic_common.h> 8 #include <gicv2.h> 9 #include <interrupt_mgmt.h> 10 11 /* 12 * The following platform GIC functions are weakly defined. They 13 * provide typical implementations that may be re-used by multiple 14 * platforms but may also be overridden by a platform if required. 15 */ 16 #pragma weak plat_ic_get_pending_interrupt_id 17 #pragma weak plat_ic_get_pending_interrupt_type 18 #pragma weak plat_ic_acknowledge_interrupt 19 #pragma weak plat_ic_get_interrupt_type 20 #pragma weak plat_ic_end_of_interrupt 21 #pragma weak plat_interrupt_type_to_line 22 23 /* 24 * This function returns the highest priority pending interrupt at 25 * the Interrupt controller 26 */ 27 uint32_t plat_ic_get_pending_interrupt_id(void) 28 { 29 unsigned int id; 30 31 id = gicv2_get_pending_interrupt_id(); 32 if (id == GIC_SPURIOUS_INTERRUPT) 33 return INTR_ID_UNAVAILABLE; 34 35 return id; 36 } 37 38 /* 39 * This function returns the type of the highest priority pending interrupt 40 * at the Interrupt controller. In the case of GICv2, the Highest Priority 41 * Pending interrupt register (`GICC_HPPIR`) is read to determine the id of 42 * the pending interrupt. The type of interrupt depends upon the id value 43 * as follows. 44 * 1. id < PENDING_G1_INTID (1022) is reported as a S-EL1 interrupt 45 * 2. id = PENDING_G1_INTID (1022) is reported as a Non-secure interrupt. 46 * 3. id = GIC_SPURIOUS_INTERRUPT (1023) is reported as an invalid interrupt 47 * type. 48 */ 49 uint32_t plat_ic_get_pending_interrupt_type(void) 50 { 51 unsigned int id; 52 53 id = gicv2_get_pending_interrupt_type(); 54 55 /* Assume that all secure interrupts are S-EL1 interrupts */ 56 if (id < PENDING_G1_INTID) 57 return INTR_TYPE_S_EL1; 58 59 if (id == GIC_SPURIOUS_INTERRUPT) 60 return INTR_TYPE_INVAL; 61 62 return INTR_TYPE_NS; 63 } 64 65 /* 66 * This function returns the highest priority pending interrupt at 67 * the Interrupt controller and indicates to the Interrupt controller 68 * that the interrupt processing has started. 69 */ 70 uint32_t plat_ic_acknowledge_interrupt(void) 71 { 72 return gicv2_acknowledge_interrupt(); 73 } 74 75 /* 76 * This function returns the type of the interrupt `id`, depending on how 77 * the interrupt has been configured in the interrupt controller 78 */ 79 uint32_t plat_ic_get_interrupt_type(uint32_t id) 80 { 81 unsigned int type; 82 83 type = gicv2_get_interrupt_group(id); 84 85 /* Assume that all secure interrupts are S-EL1 interrupts */ 86 return (type) ? INTR_TYPE_NS : INTR_TYPE_S_EL1; 87 } 88 89 /* 90 * This functions is used to indicate to the interrupt controller that 91 * the processing of the interrupt corresponding to the `id` has 92 * finished. 93 */ 94 void plat_ic_end_of_interrupt(uint32_t id) 95 { 96 gicv2_end_of_interrupt(id); 97 } 98 99 /* 100 * An ARM processor signals interrupt exceptions through the IRQ and FIQ pins. 101 * The interrupt controller knows which pin/line it uses to signal a type of 102 * interrupt. It lets the interrupt management framework determine 103 * for a type of interrupt and security state, which line should be used in the 104 * SCR_EL3 to control its routing to EL3. The interrupt line is represented 105 * as the bit position of the IRQ or FIQ bit in the SCR_EL3. 106 */ 107 uint32_t plat_interrupt_type_to_line(uint32_t type, 108 uint32_t security_state) 109 { 110 assert(type == INTR_TYPE_S_EL1 || 111 type == INTR_TYPE_EL3 || 112 type == INTR_TYPE_NS); 113 114 /* Non-secure interrupts are signaled on the IRQ line always */ 115 if (type == INTR_TYPE_NS) 116 return __builtin_ctz(SCR_IRQ_BIT); 117 118 /* 119 * Secure interrupts are signaled using the IRQ line if the FIQ is 120 * not enabled else they are signaled using the FIQ line. 121 */ 122 return ((gicv2_is_fiq_enabled()) ? __builtin_ctz(SCR_FIQ_BIT) : 123 __builtin_ctz(SCR_IRQ_BIT)); 124 } 125