1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <context.h> 10#include <cpu_data.h> 11#include <interrupt_mgmt.h> 12#include <platform_def.h> 13#include <runtime_svc.h> 14 15 .globl runtime_exceptions 16 17 /* --------------------------------------------------------------------- 18 * This macro handles Synchronous exceptions. 19 * Only SMC exceptions are supported. 20 * --------------------------------------------------------------------- 21 */ 22 .macro handle_sync_exception 23 /* Enable the SError interrupt */ 24 msr daifclr, #DAIF_ABT_BIT 25 26 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 27 28#if ENABLE_RUNTIME_INSTRUMENTATION 29 /* 30 * Read the timestamp value and store it in per-cpu data. The value 31 * will be extracted from per-cpu data by the C level SMC handler and 32 * saved to the PMF timestamp region. 33 */ 34 mrs x30, cntpct_el0 35 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 36 mrs x29, tpidr_el3 37 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 38 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 39#endif 40 41 mrs x30, esr_el3 42 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 43 44 /* Handle SMC exceptions separately from other synchronous exceptions */ 45 cmp x30, #EC_AARCH32_SMC 46 b.eq smc_handler32 47 48 cmp x30, #EC_AARCH64_SMC 49 b.eq smc_handler64 50 51 /* Other kinds of synchronous exceptions are not handled */ 52 no_ret report_unhandled_exception 53 .endm 54 55 56 /* --------------------------------------------------------------------- 57 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 58 * interrupts. 59 * --------------------------------------------------------------------- 60 */ 61 .macro handle_interrupt_exception label 62 /* Enable the SError interrupt */ 63 msr daifclr, #DAIF_ABT_BIT 64 65 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 66 bl save_gp_registers 67 68 /* Save the EL3 system registers needed to return from this exception */ 69 mrs x0, spsr_el3 70 mrs x1, elr_el3 71 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 72 73 /* Switch to the runtime stack i.e. SP_EL0 */ 74 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 75 mov x20, sp 76 msr spsel, #0 77 mov sp, x2 78 79 /* 80 * Find out whether this is a valid interrupt type. 81 * If the interrupt controller reports a spurious interrupt then return 82 * to where we came from. 83 */ 84 bl plat_ic_get_pending_interrupt_type 85 cmp x0, #INTR_TYPE_INVAL 86 b.eq interrupt_exit_\label 87 88 /* 89 * Get the registered handler for this interrupt type. 90 * A NULL return value could be 'cause of the following conditions: 91 * 92 * a. An interrupt of a type was routed correctly but a handler for its 93 * type was not registered. 94 * 95 * b. An interrupt of a type was not routed correctly so a handler for 96 * its type was not registered. 97 * 98 * c. An interrupt of a type was routed correctly to EL3, but was 99 * deasserted before its pending state could be read. Another 100 * interrupt of a different type pended at the same time and its 101 * type was reported as pending instead. However, a handler for this 102 * type was not registered. 103 * 104 * a. and b. can only happen due to a programming error. The 105 * occurrence of c. could be beyond the control of Trusted Firmware. 106 * It makes sense to return from this exception instead of reporting an 107 * error. 108 */ 109 bl get_interrupt_type_handler 110 cbz x0, interrupt_exit_\label 111 mov x21, x0 112 113 mov x0, #INTR_ID_UNAVAILABLE 114 115 /* Set the current security state in the 'flags' parameter */ 116 mrs x2, scr_el3 117 ubfx x1, x2, #0, #1 118 119 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 120 mov x2, x20 121 122 /* x3 will point to a cookie (not used now) */ 123 mov x3, xzr 124 125 /* Call the interrupt type handler */ 126 blr x21 127 128interrupt_exit_\label: 129 /* Return from exception, possibly in a different security state */ 130 b el3_exit 131 132 .endm 133 134 135 .macro save_x18_to_x29_sp_el0 136 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 137 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 138 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 139 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 140 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 141 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 142 mrs x18, sp_el0 143 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 144 .endm 145 146 147vector_base runtime_exceptions 148 149 /* --------------------------------------------------------------------- 150 * Current EL with SP_EL0 : 0x0 - 0x200 151 * --------------------------------------------------------------------- 152 */ 153vector_entry sync_exception_sp_el0 154 /* We don't expect any synchronous exceptions from EL3 */ 155 no_ret report_unhandled_exception 156 check_vector_size sync_exception_sp_el0 157 158vector_entry irq_sp_el0 159 /* 160 * EL3 code is non-reentrant. Any asynchronous exception is a serious 161 * error. Loop infinitely. 162 */ 163 no_ret report_unhandled_interrupt 164 check_vector_size irq_sp_el0 165 166 167vector_entry fiq_sp_el0 168 no_ret report_unhandled_interrupt 169 check_vector_size fiq_sp_el0 170 171 172vector_entry serror_sp_el0 173 no_ret report_unhandled_exception 174 check_vector_size serror_sp_el0 175 176 /* --------------------------------------------------------------------- 177 * Current EL with SP_ELx: 0x200 - 0x400 178 * --------------------------------------------------------------------- 179 */ 180vector_entry sync_exception_sp_elx 181 /* 182 * This exception will trigger if anything went wrong during a previous 183 * exception entry or exit or while handling an earlier unexpected 184 * synchronous exception. There is a high probability that SP_EL3 is 185 * corrupted. 186 */ 187 no_ret report_unhandled_exception 188 check_vector_size sync_exception_sp_elx 189 190vector_entry irq_sp_elx 191 no_ret report_unhandled_interrupt 192 check_vector_size irq_sp_elx 193 194vector_entry fiq_sp_elx 195 no_ret report_unhandled_interrupt 196 check_vector_size fiq_sp_elx 197 198vector_entry serror_sp_elx 199 no_ret report_unhandled_exception 200 check_vector_size serror_sp_elx 201 202 /* --------------------------------------------------------------------- 203 * Lower EL using AArch64 : 0x400 - 0x600 204 * --------------------------------------------------------------------- 205 */ 206vector_entry sync_exception_aarch64 207 /* 208 * This exception vector will be the entry point for SMCs and traps 209 * that are unhandled at lower ELs most commonly. SP_EL3 should point 210 * to a valid cpu context where the general purpose and system register 211 * state can be saved. 212 */ 213 handle_sync_exception 214 check_vector_size sync_exception_aarch64 215 216vector_entry irq_aarch64 217 handle_interrupt_exception irq_aarch64 218 check_vector_size irq_aarch64 219 220vector_entry fiq_aarch64 221 handle_interrupt_exception fiq_aarch64 222 check_vector_size fiq_aarch64 223 224vector_entry serror_aarch64 225 /* 226 * SError exceptions from lower ELs are not currently supported. 227 * Report their occurrence. 228 */ 229 no_ret report_unhandled_exception 230 check_vector_size serror_aarch64 231 232 /* --------------------------------------------------------------------- 233 * Lower EL using AArch32 : 0x600 - 0x800 234 * --------------------------------------------------------------------- 235 */ 236vector_entry sync_exception_aarch32 237 /* 238 * This exception vector will be the entry point for SMCs and traps 239 * that are unhandled at lower ELs most commonly. SP_EL3 should point 240 * to a valid cpu context where the general purpose and system register 241 * state can be saved. 242 */ 243 handle_sync_exception 244 check_vector_size sync_exception_aarch32 245 246vector_entry irq_aarch32 247 handle_interrupt_exception irq_aarch32 248 check_vector_size irq_aarch32 249 250vector_entry fiq_aarch32 251 handle_interrupt_exception fiq_aarch32 252 check_vector_size fiq_aarch32 253 254vector_entry serror_aarch32 255 /* 256 * SError exceptions from lower ELs are not currently supported. 257 * Report their occurrence. 258 */ 259 no_ret report_unhandled_exception 260 check_vector_size serror_aarch32 261 262 263 /* --------------------------------------------------------------------- 264 * The following code handles secure monitor calls. 265 * Depending upon the execution state from where the SMC has been 266 * invoked, it frees some general purpose registers to perform the 267 * remaining tasks. They involve finding the runtime service handler 268 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 269 * before calling the handler. 270 * 271 * Note that x30 has been explicitly saved and can be used here 272 * --------------------------------------------------------------------- 273 */ 274func smc_handler 275smc_handler32: 276 /* Check whether aarch32 issued an SMC64 */ 277 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 278 279 /* 280 * Since we're are coming from aarch32, x8-x18 need to be saved as per 281 * SMC32 calling convention. If a lower EL in aarch64 is making an 282 * SMC32 call then it must have saved x8-x17 already therein. 283 */ 284 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 285 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 286 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 287 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 288 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 289 290 /* x4-x7, x18, sp_el0 are saved below */ 291 292smc_handler64: 293 /* 294 * Populate the parameters for the SMC handler. 295 * We already have x0-x4 in place. x5 will point to a cookie (not used 296 * now). x6 will point to the context structure (SP_EL3) and x7 will 297 * contain flags we need to pass to the handler Hence save x5-x7. 298 * 299 * Note: x4 only needs to be preserved for AArch32 callers but we do it 300 * for AArch64 callers as well for convenience 301 */ 302 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 303 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 304 305 /* Save rest of the gpregs and sp_el0*/ 306 save_x18_to_x29_sp_el0 307 308 mov x5, xzr 309 mov x6, sp 310 311 /* Get the unique owning entity number */ 312 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 313 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 314 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 315 316 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 317 318 /* Load descriptor index from array of indices */ 319 adr x14, rt_svc_descs_indices 320 ldrb w15, [x14, x16] 321 322 /* 323 * Restore the saved C runtime stack value which will become the new 324 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 325 * structure prior to the last ERET from EL3. 326 */ 327 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 328 329 /* 330 * Any index greater than 127 is invalid. Check bit 7 for 331 * a valid index 332 */ 333 tbnz w15, 7, smc_unknown 334 335 /* Switch to SP_EL0 */ 336 msr spsel, #0 337 338 /* 339 * Get the descriptor using the index 340 * x11 = (base + off), x15 = index 341 * 342 * handler = (base + off) + (index << log2(size)) 343 */ 344 lsl w10, w15, #RT_SVC_SIZE_LOG2 345 ldr x15, [x11, w10, uxtw] 346 347 /* 348 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 349 * switch during SMC handling. 350 * TODO: Revisit if all system registers can be saved later. 351 */ 352 mrs x16, spsr_el3 353 mrs x17, elr_el3 354 mrs x18, scr_el3 355 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 356 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 357 358 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 359 bfi x7, x18, #0, #1 360 361 mov sp, x12 362 363 /* 364 * Call the Secure Monitor Call handler and then drop directly into 365 * el3_exit() which will program any remaining architectural state 366 * prior to issuing the ERET to the desired lower EL. 367 */ 368#if DEBUG 369 cbz x15, rt_svc_fw_critical_error 370#endif 371 blr x15 372 373 b el3_exit 374 375smc_unknown: 376 /* 377 * Here we restore x4-x18 regardless of where we came from. AArch32 378 * callers will find the registers contents unchanged, but AArch64 379 * callers will find the registers modified (with stale earlier NS 380 * content). Either way, we aren't leaking any secure information 381 * through them. 382 */ 383 mov w0, #SMC_UNK 384 b restore_gp_registers_callee_eret 385 386smc_prohibited: 387 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 388 mov w0, #SMC_UNK 389 eret 390 391rt_svc_fw_critical_error: 392 /* Switch to SP_ELx */ 393 msr spsel, #1 394 no_ret report_unhandled_exception 395endfunc smc_handler 396