1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <plat/common/common_def.h> 12 13 /* CPU topology */ 14 #define PLAT_MAX_CORES_PER_CLUSTER 2 15 #define PLAT_CLUSTER_COUNT 12 16 #define PLATFORM_CORE_COUNT (PLAT_CLUSTER_COUNT * \ 17 PLAT_MAX_CORES_PER_CLUSTER) 18 19 #define PLAT_MAX_PWR_LVL U(1) 20 #define PLAT_MAX_RET_STATE U(1) 21 #define PLAT_MAX_OFF_STATE U(2) 22 23 #define SQ_LOCAL_STATE_RUN 0 24 #define SQ_LOCAL_STATE_RET 1 25 #define SQ_LOCAL_STATE_OFF 2 26 27 #define CACHE_WRITEBACK_SHIFT 6 28 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 29 30 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 31 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 32 #define MAX_XLAT_TABLES 4 33 #define MAX_MMAP_REGIONS 6 34 35 #define PLATFORM_STACK_SIZE 0x400 36 37 #define BL31_BASE 0x04000000 38 #define BL31_SIZE 0x00080000 39 #define BL31_LIMIT (BL31_BASE + BL31_SIZE) 40 41 #define PLAT_SQ_CCN_BASE 0x32000000 42 #define PLAT_SQ_CLUSTER_TO_CCN_ID_MAP \ 43 0, /* Cluster 0 */ \ 44 18, /* Cluster 1 */ \ 45 11, /* Cluster 2 */ \ 46 29, /* Cluster 3 */ \ 47 35, /* Cluster 4 */ \ 48 17, /* Cluster 5 */ \ 49 12, /* Cluster 6 */ \ 50 30, /* Cluster 7 */ \ 51 14, /* Cluster 8 */ \ 52 32, /* Cluster 9 */ \ 53 15, /* Cluster 10 */ \ 54 33 /* Cluster 11 */ 55 56 /* UART related constants */ 57 #define PLAT_SQ_BOOT_UART_BASE 0x2A400000 58 #define PLAT_SQ_BOOT_UART_CLK_IN_HZ 62500000 59 #define SQ_CONSOLE_BAUDRATE 115200 60 61 #define SQ_SYS_CNTCTL_BASE 0x2a430000 62 63 #define SQ_SYS_TIMCTL_BASE 0x2a810000 64 #define PLAT_SQ_NSTIMER_FRAME_ID 0 65 66 #define DRAMINFO_BASE 0x2E00FFC0 67 68 #define PLAT_SQ_MHU_BASE 0x45000000 69 70 #define PLAT_SQ_SCP_COM_SHARED_MEM_BASE 0x45400000 71 #define SCPI_CMD_GET_DRAMINFO 0x1 72 73 #define SQ_BOOT_CFG_ADDR 0x45410000 74 #define PLAT_SQ_PRIMARY_CPU_SHIFT 8 75 #define PLAT_SQ_PRIMARY_CPU_BIT_WIDTH 6 76 77 #define PLAT_SQ_GICD_BASE 0x30000000 78 #define PLAT_SQ_GICR_BASE 0x30400000 79 80 #define PLAT_SQ_GPIO_BASE 0x51000000 81 82 #endif /* PLATFORM_DEF_H */ 83