1 /* 2 * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32_I2C_H 8 #define STM32_I2C_H 9 10 #include <stdint.h> 11 12 #include <lib/utils_def.h> 13 14 /* Bit definition for I2C_CR1 register */ 15 #define I2C_CR1_PE BIT(0) 16 #define I2C_CR1_TXIE BIT(1) 17 #define I2C_CR1_RXIE BIT(2) 18 #define I2C_CR1_ADDRIE BIT(3) 19 #define I2C_CR1_NACKIE BIT(4) 20 #define I2C_CR1_STOPIE BIT(5) 21 #define I2C_CR1_TCIE BIT(6) 22 #define I2C_CR1_ERRIE BIT(7) 23 #define I2C_CR1_DNF GENMASK(11, 8) 24 #define I2C_CR1_ANFOFF BIT(12) 25 #define I2C_CR1_SWRST BIT(13) 26 #define I2C_CR1_TXDMAEN BIT(14) 27 #define I2C_CR1_RXDMAEN BIT(15) 28 #define I2C_CR1_SBC BIT(16) 29 #define I2C_CR1_NOSTRETCH BIT(17) 30 #define I2C_CR1_WUPEN BIT(18) 31 #define I2C_CR1_GCEN BIT(19) 32 #define I2C_CR1_SMBHEN BIT(22) 33 #define I2C_CR1_SMBDEN BIT(21) 34 #define I2C_CR1_ALERTEN BIT(22) 35 #define I2C_CR1_PECEN BIT(23) 36 37 /* Bit definition for I2C_CR2 register */ 38 #define I2C_CR2_SADD GENMASK(9, 0) 39 #define I2C_CR2_RD_WRN BIT(10) 40 #define I2C_CR2_RD_WRN_OFFSET 10U 41 #define I2C_CR2_ADD10 BIT(11) 42 #define I2C_CR2_HEAD10R BIT(12) 43 #define I2C_CR2_START BIT(13) 44 #define I2C_CR2_STOP BIT(14) 45 #define I2C_CR2_NACK BIT(15) 46 #define I2C_CR2_NBYTES GENMASK(23, 16) 47 #define I2C_CR2_NBYTES_OFFSET 16U 48 #define I2C_CR2_RELOAD BIT(24) 49 #define I2C_CR2_AUTOEND BIT(25) 50 #define I2C_CR2_PECBYTE BIT(26) 51 52 /* Bit definition for I2C_OAR1 register */ 53 #define I2C_OAR1_OA1 GENMASK(9, 0) 54 #define I2C_OAR1_OA1MODE BIT(10) 55 #define I2C_OAR1_OA1EN BIT(15) 56 57 /* Bit definition for I2C_OAR2 register */ 58 #define I2C_OAR2_OA2 GENMASK(7, 1) 59 #define I2C_OAR2_OA2MSK GENMASK(10, 8) 60 #define I2C_OAR2_OA2NOMASK 0 61 #define I2C_OAR2_OA2MASK01 BIT(8) 62 #define I2C_OAR2_OA2MASK02 BIT(9) 63 #define I2C_OAR2_OA2MASK03 GENMASK(9, 8) 64 #define I2C_OAR2_OA2MASK04 BIT(10) 65 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 66 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 67 #define I2C_OAR2_OA2MASK07 GENMASK(10, 8) 68 #define I2C_OAR2_OA2EN BIT(15) 69 70 /* Bit definition for I2C_TIMINGR register */ 71 #define I2C_TIMINGR_SCLL GENMASK(7, 0) 72 #define I2C_TIMINGR_SCLH GENMASK(15, 8) 73 #define I2C_TIMINGR_SDADEL GENMASK(19, 16) 74 #define I2C_TIMINGR_SCLDEL GENMASK(23, 20) 75 #define I2C_TIMINGR_PRESC GENMASK(31, 28) 76 77 /* Bit definition for I2C_TIMEOUTR register */ 78 #define I2C_TIMEOUTR_TIMEOUTA GENMASK(11, 0) 79 #define I2C_TIMEOUTR_TIDLE BIT(12) 80 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 81 #define I2C_TIMEOUTR_TIMEOUTB GENMASK(27, 16) 82 #define I2C_TIMEOUTR_TEXTEN BIT(31) 83 84 /* Bit definition for I2C_ISR register */ 85 #define I2C_ISR_TXE BIT(0) 86 #define I2C_ISR_TXIS BIT(1) 87 #define I2C_ISR_RXNE BIT(2) 88 #define I2C_ISR_ADDR BIT(3) 89 #define I2C_ISR_NACKF BIT(4) 90 #define I2C_ISR_STOPF BIT(5) 91 #define I2C_ISR_TC BIT(6) 92 #define I2C_ISR_TCR BIT(7) 93 #define I2C_ISR_BERR BIT(8) 94 #define I2C_ISR_ARLO BIT(9) 95 #define I2C_ISR_OVR BIT(10) 96 #define I2C_ISR_PECERR BIT(11) 97 #define I2C_ISR_TIMEOUT BIT(12) 98 #define I2C_ISR_ALERT BIT(13) 99 #define I2C_ISR_BUSY BIT(15) 100 #define I2C_ISR_DIR BIT(16) 101 #define I2C_ISR_ADDCODE GENMASK(23, 17) 102 103 /* Bit definition for I2C_ICR register */ 104 #define I2C_ICR_ADDRCF BIT(3) 105 #define I2C_ICR_NACKCF BIT(4) 106 #define I2C_ICR_STOPCF BIT(5) 107 #define I2C_ICR_BERRCF BIT(8) 108 #define I2C_ICR_ARLOCF BIT(9) 109 #define I2C_ICR_OVRCF BIT(10) 110 #define I2C_ICR_PECCF BIT(11) 111 #define I2C_ICR_TIMOUTCF BIT(12) 112 #define I2C_ICR_ALERTCF BIT(13) 113 114 struct stm32_i2c_init_s { 115 uint32_t timing; /* Specifies the I2C_TIMINGR_register value 116 * This parameter is calculated by referring 117 * to I2C initialization section in Reference 118 * manual. 119 */ 120 121 uint32_t own_address1; /* Specifies the first device own address. 122 * This parameter can be a 7-bit or 10-bit 123 * address. 124 */ 125 126 uint32_t addressing_mode; /* Specifies if 7-bit or 10-bit addressing 127 * mode is selected. 128 * This parameter can be a value of @ref 129 * I2C_ADDRESSING_MODE. 130 */ 131 132 uint32_t dual_address_mode; /* Specifies if dual addressing mode is 133 * selected. 134 * This parameter can be a value of @ref 135 * I2C_DUAL_ADDRESSING_MODE. 136 */ 137 138 uint32_t own_address2; /* Specifies the second device own address 139 * if dual addressing mode is selected. 140 * This parameter can be a 7-bit address. 141 */ 142 143 uint32_t own_address2_masks; /* Specifies the acknowledge mask address 144 * second device own address if dual 145 * addressing mode is selected. 146 * This parameter can be a value of @ref 147 * I2C_OWN_ADDRESS2_MASKS. 148 */ 149 150 uint32_t general_call_mode; /* Specifies if general call mode is 151 * selected. 152 * This parameter can be a value of @ref 153 * I2C_GENERAL_CALL_ADDRESSING_MODE. 154 */ 155 156 uint32_t no_stretch_mode; /* Specifies if nostretch mode is 157 * selected. 158 * This parameter can be a value of @ref 159 * I2C_NOSTRETCH_MODE. 160 */ 161 162 }; 163 164 enum i2c_state_e { 165 I2C_STATE_RESET = 0x00U, /* Peripheral is not yet 166 * initialized. 167 */ 168 I2C_STATE_READY = 0x20U, /* Peripheral Initialized 169 * and ready for use. 170 */ 171 I2C_STATE_BUSY = 0x24U, /* An internal process is 172 * ongoing. 173 */ 174 I2C_STATE_BUSY_TX = 0x21U, /* Data Transmission process 175 * is ongoing. 176 */ 177 I2C_STATE_BUSY_RX = 0x22U, /* Data Reception process 178 * is ongoing. 179 */ 180 I2C_STATE_LISTEN = 0x28U, /* Address Listen Mode is 181 * ongoing. 182 */ 183 I2C_STATE_BUSY_TX_LISTEN = 0x29U, /* Address Listen Mode 184 * and Data Transmission 185 * process is ongoing. 186 */ 187 I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /* Address Listen Mode 188 * and Data Reception 189 * process is ongoing. 190 */ 191 I2C_STATE_ABORT = 0x60U, /* Abort user request ongoing. */ 192 I2C_STATE_TIMEOUT = 0xA0U, /* Timeout state. */ 193 I2C_STATE_ERROR = 0xE0U /* Error. */ 194 195 }; 196 197 enum i2c_mode_e { 198 I2C_MODE_NONE = 0x00U, /* No I2C communication on going. */ 199 I2C_MODE_MASTER = 0x10U, /* I2C communication is in Master Mode. */ 200 I2C_MODE_SLAVE = 0x20U, /* I2C communication is in Slave Mode. */ 201 I2C_MODE_MEM = 0x40U /* I2C communication is in Memory Mode. */ 202 203 }; 204 205 #define I2C_ERROR_NONE 0x00000000U /* No error */ 206 #define I2C_ERROR_BERR 0x00000001U /* BERR error */ 207 #define I2C_ERROR_ARLO 0x00000002U /* ARLO error */ 208 #define I2C_ERROR_AF 0x00000004U /* ACKF error */ 209 #define I2C_ERROR_OVR 0x00000008U /* OVR error */ 210 #define I2C_ERROR_DMA 0x00000010U /* DMA transfer error */ 211 #define I2C_ERROR_TIMEOUT 0x00000020U /* Timeout error */ 212 #define I2C_ERROR_SIZE 0x00000040U /* Size Management error */ 213 214 struct i2c_handle_s { 215 uint32_t i2c_base_addr; /* Registers base address */ 216 217 struct stm32_i2c_init_s i2c_init; /* Communication parameters */ 218 219 uint8_t *p_buff; /* Pointer to transfer buffer */ 220 221 uint16_t xfer_size; /* Transfer size */ 222 223 uint16_t xfer_count; /* Transfer counter */ 224 225 uint32_t prev_state; /* Communication previous 226 * state 227 */ 228 229 uint8_t lock; /* Locking object */ 230 231 enum i2c_state_e i2c_state; /* Communication state */ 232 233 enum i2c_mode_e i2c_mode; /* Communication mode */ 234 235 uint32_t i2c_err; /* Error code */ 236 }; 237 238 #define I2C_ADDRESSINGMODE_7BIT 0x00000001U 239 #define I2C_ADDRESSINGMODE_10BIT 0x00000002U 240 241 #define I2C_DUALADDRESS_DISABLE 0x00000000U 242 #define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 243 244 #define I2C_GENERALCALL_DISABLE 0x00000000U 245 #define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN 246 247 #define I2C_NOSTRETCH_DISABLE 0x00000000U 248 #define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 249 250 #define I2C_MEMADD_SIZE_8BIT 0x00000001U 251 #define I2C_MEMADD_SIZE_16BIT 0x00000002U 252 253 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 254 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 255 #define I2C_SOFTEND_MODE 0x00000000U 256 257 #define I2C_NO_STARTSTOP 0x00000000U 258 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 259 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 260 I2C_CR2_RD_WRN) 261 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 262 263 #define I2C_FLAG_TXE I2C_ISR_TXE 264 #define I2C_FLAG_TXIS I2C_ISR_TXIS 265 #define I2C_FLAG_RXNE I2C_ISR_RXNE 266 #define I2C_FLAG_ADDR I2C_ISR_ADDR 267 #define I2C_FLAG_AF I2C_ISR_NACKF 268 #define I2C_FLAG_STOPF I2C_ISR_STOPF 269 #define I2C_FLAG_TC I2C_ISR_TC 270 #define I2C_FLAG_TCR I2C_ISR_TCR 271 #define I2C_FLAG_BERR I2C_ISR_BERR 272 #define I2C_FLAG_ARLO I2C_ISR_ARLO 273 #define I2C_FLAG_OVR I2C_ISR_OVR 274 #define I2C_FLAG_PECERR I2C_ISR_PECERR 275 #define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT 276 #define I2C_FLAG_ALERT I2C_ISR_ALERT 277 #define I2C_FLAG_BUSY I2C_ISR_BUSY 278 #define I2C_FLAG_DIR I2C_ISR_DIR 279 280 #define I2C_RESET_CR2 (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 281 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 282 I2C_CR2_RD_WRN) 283 284 #define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U) 285 #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 286 287 int stm32_i2c_init(struct i2c_handle_s *hi2c); 288 289 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint16_t dev_addr, 290 uint16_t mem_addr, uint16_t mem_add_size, 291 uint8_t *p_data, uint16_t size, uint32_t timeout); 292 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint16_t dev_addr, 293 uint16_t mem_addr, uint16_t mem_add_size, 294 uint8_t *p_data, uint16_t size, uint32_t timeout); 295 int stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint16_t dev_addr, 296 uint32_t trials, uint32_t timeout); 297 298 int stm32_i2c_config_analog_filter(struct i2c_handle_s *hi2c, 299 uint32_t analog_filter); 300 301 #endif /* STM32_I2C_H */ 302