1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TSPD_PRIVATE_H__ 8 #define __TSPD_PRIVATE_H__ 9 10 #include <arch.h> 11 #include <context.h> 12 #include <interrupt_mgmt.h> 13 #include <platform_def.h> 14 #include <psci.h> 15 16 /******************************************************************************* 17 * Secure Payload PM state information e.g. SP is suspended, uninitialised etc 18 * and macros to access the state information in the per-cpu 'state' flags 19 ******************************************************************************/ 20 #define TSP_PSTATE_OFF 0 21 #define TSP_PSTATE_ON 1 22 #define TSP_PSTATE_SUSPEND 2 23 #define TSP_PSTATE_SHIFT 0 24 #define TSP_PSTATE_MASK 0x3 25 #define get_tsp_pstate(state) ((state >> TSP_PSTATE_SHIFT) & TSP_PSTATE_MASK) 26 #define clr_tsp_pstate(state) (state &= ~(TSP_PSTATE_MASK \ 27 << TSP_PSTATE_SHIFT)) 28 #define set_tsp_pstate(st, pst) do { \ 29 clr_tsp_pstate(st); \ 30 st |= (pst & TSP_PSTATE_MASK) << \ 31 TSP_PSTATE_SHIFT; \ 32 } while (0); 33 34 35 /* 36 * This flag is used by the TSPD to determine if the TSP is servicing a standard 37 * SMC request prior to programming the next entry into the TSP e.g. if TSP 38 * execution is preempted by a non-secure interrupt and handed control to the 39 * normal world. If another request which is distinct from what the TSP was 40 * previously doing arrives, then this flag will be help the TSPD to either 41 * reject the new request or service it while ensuring that the previous context 42 * is not corrupted. 43 */ 44 #define STD_SMC_ACTIVE_FLAG_SHIFT 2 45 #define STD_SMC_ACTIVE_FLAG_MASK 1 46 #define get_std_smc_active_flag(state) ((state >> STD_SMC_ACTIVE_FLAG_SHIFT) \ 47 & STD_SMC_ACTIVE_FLAG_MASK) 48 #define set_std_smc_active_flag(state) (state |= \ 49 1 << STD_SMC_ACTIVE_FLAG_SHIFT) 50 #define clr_std_smc_active_flag(state) (state &= \ 51 ~(STD_SMC_ACTIVE_FLAG_MASK \ 52 << STD_SMC_ACTIVE_FLAG_SHIFT)) 53 54 /******************************************************************************* 55 * Secure Payload execution state information i.e. aarch32 or aarch64 56 ******************************************************************************/ 57 #define TSP_AARCH32 MODE_RW_32 58 #define TSP_AARCH64 MODE_RW_64 59 60 /******************************************************************************* 61 * The SPD should know the type of Secure Payload. 62 ******************************************************************************/ 63 #define TSP_TYPE_UP PSCI_TOS_NOT_UP_MIG_CAP 64 #define TSP_TYPE_UPM PSCI_TOS_UP_MIG_CAP 65 #define TSP_TYPE_MP PSCI_TOS_NOT_PRESENT_MP 66 67 /******************************************************************************* 68 * Secure Payload migrate type information as known to the SPD. We assume that 69 * the SPD is dealing with an MP Secure Payload. 70 ******************************************************************************/ 71 #define TSP_MIGRATE_INFO TSP_TYPE_MP 72 73 /******************************************************************************* 74 * Number of cpus that the present on this platform. TODO: Rely on a topology 75 * tree to determine this in the future to avoid assumptions about mpidr 76 * allocation 77 ******************************************************************************/ 78 #define TSPD_CORE_COUNT PLATFORM_CORE_COUNT 79 80 /******************************************************************************* 81 * Constants that allow assembler code to preserve callee-saved registers of the 82 * C runtime context while performing a security state switch. 83 ******************************************************************************/ 84 #define TSPD_C_RT_CTX_X19 0x0 85 #define TSPD_C_RT_CTX_X20 0x8 86 #define TSPD_C_RT_CTX_X21 0x10 87 #define TSPD_C_RT_CTX_X22 0x18 88 #define TSPD_C_RT_CTX_X23 0x20 89 #define TSPD_C_RT_CTX_X24 0x28 90 #define TSPD_C_RT_CTX_X25 0x30 91 #define TSPD_C_RT_CTX_X26 0x38 92 #define TSPD_C_RT_CTX_X27 0x40 93 #define TSPD_C_RT_CTX_X28 0x48 94 #define TSPD_C_RT_CTX_X29 0x50 95 #define TSPD_C_RT_CTX_X30 0x58 96 #define TSPD_C_RT_CTX_SIZE 0x60 97 #define TSPD_C_RT_CTX_ENTRIES (TSPD_C_RT_CTX_SIZE >> DWORD_SHIFT) 98 99 /******************************************************************************* 100 * Constants that allow assembler code to preserve caller-saved registers of the 101 * SP context while performing a TSP preemption. 102 * Note: These offsets have to match with the offsets for the corresponding 103 * registers in cpu_context as we are using memcpy to copy the values from 104 * cpu_context to sp_ctx. 105 ******************************************************************************/ 106 #define TSPD_SP_CTX_X0 0x0 107 #define TSPD_SP_CTX_X1 0x8 108 #define TSPD_SP_CTX_X2 0x10 109 #define TSPD_SP_CTX_X3 0x18 110 #define TSPD_SP_CTX_X4 0x20 111 #define TSPD_SP_CTX_X5 0x28 112 #define TSPD_SP_CTX_X6 0x30 113 #define TSPD_SP_CTX_X7 0x38 114 #define TSPD_SP_CTX_X8 0x40 115 #define TSPD_SP_CTX_X9 0x48 116 #define TSPD_SP_CTX_X10 0x50 117 #define TSPD_SP_CTX_X11 0x58 118 #define TSPD_SP_CTX_X12 0x60 119 #define TSPD_SP_CTX_X13 0x68 120 #define TSPD_SP_CTX_X14 0x70 121 #define TSPD_SP_CTX_X15 0x78 122 #define TSPD_SP_CTX_X16 0x80 123 #define TSPD_SP_CTX_X17 0x88 124 #define TSPD_SP_CTX_SIZE 0x90 125 #define TSPD_SP_CTX_ENTRIES (TSPD_SP_CTX_SIZE >> DWORD_SHIFT) 126 127 #ifndef __ASSEMBLY__ 128 129 #include <cassert.h> 130 #include <stdint.h> 131 132 /* 133 * The number of arguments to save during a SMC call for TSP. 134 * Currently only x1 and x2 are used by TSP. 135 */ 136 #define TSP_NUM_ARGS 0x2 137 138 /* AArch64 callee saved general purpose register context structure. */ 139 DEFINE_REG_STRUCT(c_rt_regs, TSPD_C_RT_CTX_ENTRIES); 140 141 /* 142 * Compile time assertion to ensure that both the compiler and linker 143 * have the same double word aligned view of the size of the C runtime 144 * register context. 145 */ 146 CASSERT(TSPD_C_RT_CTX_SIZE == sizeof(c_rt_regs_t), \ 147 assert_spd_c_rt_regs_size_mismatch); 148 149 /* SEL1 Secure payload (SP) caller saved register context structure. */ 150 DEFINE_REG_STRUCT(sp_ctx_regs, TSPD_SP_CTX_ENTRIES); 151 152 /* 153 * Compile time assertion to ensure that both the compiler and linker 154 * have the same double word aligned view of the size of the C runtime 155 * register context. 156 */ 157 CASSERT(TSPD_SP_CTX_SIZE == sizeof(sp_ctx_regs_t), \ 158 assert_spd_sp_regs_size_mismatch); 159 160 /******************************************************************************* 161 * Structure which helps the SPD to maintain the per-cpu state of the SP. 162 * 'saved_spsr_el3' - temporary copy to allow S-EL1 interrupt handling when 163 * the TSP has been preempted. 164 * 'saved_elr_el3' - temporary copy to allow S-EL1 interrupt handling when 165 * the TSP has been preempted. 166 * 'state' - collection of flags to track SP state e.g. on/off 167 * 'mpidr' - mpidr to associate a context with a cpu 168 * 'c_rt_ctx' - stack address to restore C runtime context from after 169 * returning from a synchronous entry into the SP. 170 * 'cpu_ctx' - space to maintain SP architectural state 171 * 'saved_tsp_args' - space to store arguments for TSP arithmetic operations 172 * which will queried using the TSP_GET_ARGS SMC by TSP. 173 * 'sp_ctx' - space to save the SEL1 Secure Payload(SP) caller saved 174 * register context after it has been preempted by an EL3 175 * routed NS interrupt and when a Secure Interrupt is taken 176 * to SP. 177 ******************************************************************************/ 178 typedef struct tsp_context { 179 uint64_t saved_elr_el3; 180 uint32_t saved_spsr_el3; 181 uint32_t state; 182 uint64_t mpidr; 183 uint64_t c_rt_ctx; 184 cpu_context_t cpu_ctx; 185 uint64_t saved_tsp_args[TSP_NUM_ARGS]; 186 #if TSP_NS_INTR_ASYNC_PREEMPT 187 sp_ctx_regs_t sp_ctx; 188 #endif 189 } tsp_context_t; 190 191 /* Helper macros to store and retrieve tsp args from tsp_context */ 192 #define store_tsp_args(tsp_ctx, x1, x2) do {\ 193 tsp_ctx->saved_tsp_args[0] = x1;\ 194 tsp_ctx->saved_tsp_args[1] = x2;\ 195 } while (0) 196 197 #define get_tsp_args(tsp_ctx, x1, x2) do {\ 198 x1 = tsp_ctx->saved_tsp_args[0];\ 199 x2 = tsp_ctx->saved_tsp_args[1];\ 200 } while (0) 201 202 /* TSPD power management handlers */ 203 extern const spd_pm_ops_t tspd_pm; 204 205 /******************************************************************************* 206 * Forward declarations 207 ******************************************************************************/ 208 struct tsp_vectors; 209 210 /******************************************************************************* 211 * Function & Data prototypes 212 ******************************************************************************/ 213 uint64_t tspd_enter_sp(uint64_t *c_rt_ctx); 214 void __dead2 tspd_exit_sp(uint64_t c_rt_ctx, uint64_t ret); 215 uint64_t tspd_synchronous_sp_entry(tsp_context_t *tsp_ctx); 216 void __dead2 tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret); 217 void tspd_init_tsp_ep_state(struct entry_point_info *tsp_ep, 218 uint32_t rw, 219 uint64_t pc, 220 tsp_context_t *tsp_ctx); 221 int tspd_abort_preempted_smc(tsp_context_t *tsp_ctx); 222 223 extern tsp_context_t tspd_sp_context[TSPD_CORE_COUNT]; 224 extern struct tsp_vectors *tsp_vectors; 225 #endif /*__ASSEMBLY__*/ 226 227 #endif /* __TSPD_PRIVATE_H__ */ 228