1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <arch_helpers.h> 10 #include <bl31/interrupt_mgmt.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <denver.h> 15 #include <lib/bakery_lock.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <plat/common/platform.h> 18 19 #include <tegra_def.h> 20 #include <tegra_private.h> 21 22 static DEFINE_BAKERY_LOCK(tegra_fiq_lock); 23 24 /******************************************************************************* 25 * Static variables 26 ******************************************************************************/ 27 static uint64_t ns_fiq_handler_addr; 28 static uint32_t fiq_handler_active; 29 static pcpu_fiq_state_t fiq_state[PLATFORM_CORE_COUNT]; 30 31 /******************************************************************************* 32 * Handler for FIQ interrupts 33 ******************************************************************************/ 34 static uint64_t tegra_fiq_interrupt_handler(uint32_t id, 35 uint32_t flags, 36 void *handle, 37 void *cookie) 38 { 39 cpu_context_t *ctx = cm_get_context(NON_SECURE); 40 el3_state_t *el3state_ctx = get_el3state_ctx(ctx); 41 uint32_t cpu = plat_my_core_pos(); 42 uint32_t irq; 43 44 bakery_lock_get(&tegra_fiq_lock); 45 46 /* 47 * The FIQ was generated when the execution was in the non-secure 48 * world. Save the context registers to start with. 49 */ 50 cm_el1_sysregs_context_save(NON_SECURE); 51 52 /* 53 * Save elr_el3 and spsr_el3 from the saved context, and overwrite 54 * the context with the NS fiq_handler_addr and SPSR value. 55 */ 56 fiq_state[cpu].elr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3)); 57 fiq_state[cpu].spsr_el3 = read_ctx_reg((el3state_ctx), (uint32_t)(CTX_SPSR_EL3)); 58 59 /* 60 * Set the new ELR to continue execution in the NS world using the 61 * FIQ handler registered earlier. 62 */ 63 assert(ns_fiq_handler_addr); 64 write_ctx_reg((el3state_ctx), (uint32_t)(CTX_ELR_EL3), (ns_fiq_handler_addr)); 65 66 /* 67 * Mark this interrupt as complete to avoid a FIQ storm. 68 */ 69 irq = plat_ic_acknowledge_interrupt(); 70 if (irq < 1022U) { 71 plat_ic_end_of_interrupt(irq); 72 } 73 74 bakery_lock_release(&tegra_fiq_lock); 75 76 return 0; 77 } 78 79 /******************************************************************************* 80 * Setup handler for FIQ interrupts 81 ******************************************************************************/ 82 void tegra_fiq_handler_setup(void) 83 { 84 uint32_t flags; 85 int32_t rc; 86 87 /* return if already registered */ 88 if (fiq_handler_active == 0U) { 89 /* 90 * Register an interrupt handler for FIQ interrupts generated for 91 * NS interrupt sources 92 */ 93 flags = 0U; 94 set_interrupt_rm_flag((flags), (NON_SECURE)); 95 rc = register_interrupt_type_handler(INTR_TYPE_EL3, 96 tegra_fiq_interrupt_handler, 97 flags); 98 if (rc != 0) { 99 panic(); 100 } 101 102 /* handler is now active */ 103 fiq_handler_active = 1; 104 } 105 } 106 107 /******************************************************************************* 108 * Validate and store NS world's entrypoint for FIQ interrupts 109 ******************************************************************************/ 110 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint) 111 { 112 ns_fiq_handler_addr = entrypoint; 113 } 114 115 /******************************************************************************* 116 * Handler to return the NS EL1/EL0 CPU context 117 ******************************************************************************/ 118 int32_t tegra_fiq_get_intr_context(void) 119 { 120 cpu_context_t *ctx = cm_get_context(NON_SECURE); 121 gp_regs_t *gpregs_ctx = get_gpregs_ctx(ctx); 122 const el1_sys_regs_t *el1state_ctx = get_sysregs_ctx(ctx); 123 uint32_t cpu = plat_my_core_pos(); 124 uint64_t val; 125 126 /* 127 * We store the ELR_EL3, SPSR_EL3, SP_EL0 and SP_EL1 registers so 128 * that el3_exit() sends these values back to the NS world. 129 */ 130 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X0), (fiq_state[cpu].elr_el3)); 131 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X1), (fiq_state[cpu].spsr_el3)); 132 133 val = read_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_SP_EL0)); 134 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X2), (val)); 135 136 val = read_ctx_reg((el1state_ctx), (uint32_t)(CTX_SP_EL1)); 137 write_ctx_reg((gpregs_ctx), (uint32_t)(CTX_GPREG_X3), (val)); 138 139 return 0; 140 } 141