1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <ccn.h> 10 #include <debug.h> 11 #include <gicv2.h> 12 #include <mmio.h> 13 #include <plat_arm.h> 14 #include <v2m_def.h> 15 #include "../fvp_def.h" 16 17 /* Defines for GIC Driver build time selection */ 18 #define FVP_GICV2 1 19 #define FVP_GICV3 2 20 #define FVP_GICV3_LEGACY 3 21 22 /******************************************************************************* 23 * arm_config holds the characteristics of the differences between the three FVP 24 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 25 * at each boot stage by the primary before enabling the MMU (to allow 26 * interconnect configuration) & used thereafter. Each BL will have its own copy 27 * to allow independent operation. 28 ******************************************************************************/ 29 arm_config_t arm_config; 30 31 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 32 DEVICE0_SIZE, \ 33 MT_DEVICE | MT_RW | MT_SECURE) 34 35 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 36 DEVICE1_SIZE, \ 37 MT_DEVICE | MT_RW | MT_SECURE) 38 39 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 40 DEVICE2_SIZE, \ 41 MT_DEVICE | MT_RW | MT_SECURE) 42 43 44 /* 45 * Table of memory regions for various BL stages to map using the MMU. 46 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 47 * takes care of mapping it. 48 * 49 * The flash needs to be mapped as writable in order to erase the FIP's Table of 50 * Contents in case of unrecoverable error (see plat_error_handler()). 51 */ 52 #ifdef IMAGE_BL1 53 const mmap_region_t plat_arm_mmap[] = { 54 ARM_MAP_SHARED_RAM, 55 V2M_MAP_FLASH0_RW, 56 V2M_MAP_IOFPGA, 57 MAP_DEVICE0, 58 MAP_DEVICE1, 59 MAP_DEVICE2, 60 #if TRUSTED_BOARD_BOOT 61 ARM_MAP_NS_DRAM1, 62 #endif 63 {0} 64 }; 65 #endif 66 #ifdef IMAGE_BL2 67 const mmap_region_t plat_arm_mmap[] = { 68 ARM_MAP_SHARED_RAM, 69 V2M_MAP_FLASH0_RW, 70 V2M_MAP_IOFPGA, 71 MAP_DEVICE0, 72 MAP_DEVICE1, 73 MAP_DEVICE2, 74 ARM_MAP_NS_DRAM1, 75 ARM_MAP_TSP_SEC_MEM, 76 #if ARM_BL31_IN_DRAM 77 ARM_MAP_BL31_SEC_DRAM, 78 #endif 79 {0} 80 }; 81 #endif 82 #ifdef IMAGE_BL2U 83 const mmap_region_t plat_arm_mmap[] = { 84 MAP_DEVICE0, 85 V2M_MAP_IOFPGA, 86 {0} 87 }; 88 #endif 89 #ifdef IMAGE_BL31 90 const mmap_region_t plat_arm_mmap[] = { 91 ARM_MAP_SHARED_RAM, 92 V2M_MAP_IOFPGA, 93 MAP_DEVICE0, 94 MAP_DEVICE1, 95 {0} 96 }; 97 #endif 98 #ifdef IMAGE_BL32 99 const mmap_region_t plat_arm_mmap[] = { 100 #ifdef AARCH32 101 ARM_MAP_SHARED_RAM, 102 #endif 103 V2M_MAP_IOFPGA, 104 MAP_DEVICE0, 105 MAP_DEVICE1, 106 {0} 107 }; 108 #endif 109 110 ARM_CASSERT_MMAP 111 112 113 /******************************************************************************* 114 * A single boot loader stack is expected to work on both the Foundation FVP 115 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 116 * SYS_ID register provides a mechanism for detecting the differences between 117 * these platforms. This information is stored in a per-BL array to allow the 118 * code to take the correct path.Per BL platform configuration. 119 ******************************************************************************/ 120 void fvp_config_setup(void) 121 { 122 unsigned int rev, hbi, bld, arch, sys_id; 123 124 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 125 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 126 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 127 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 128 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 129 130 if (arch != ARCH_MODEL) { 131 ERROR("This firmware is for FVP models\n"); 132 panic(); 133 } 134 135 /* 136 * The build field in the SYS_ID tells which variant of the GIC 137 * memory is implemented by the model. 138 */ 139 switch (bld) { 140 case BLD_GIC_VE_MMAP: 141 ERROR("Legacy Versatile Express memory map for GIC peripheral" 142 " is not supported\n"); 143 panic(); 144 break; 145 case BLD_GIC_A53A57_MMAP: 146 break; 147 default: 148 ERROR("Unsupported board build %x\n", bld); 149 panic(); 150 } 151 152 /* 153 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 154 * for the Foundation FVP. 155 */ 156 switch (hbi) { 157 case HBI_FOUNDATION_FVP: 158 arm_config.flags = 0; 159 160 /* 161 * Check for supported revisions of Foundation FVP 162 * Allow future revisions to run but emit warning diagnostic 163 */ 164 switch (rev) { 165 case REV_FOUNDATION_FVP_V2_0: 166 case REV_FOUNDATION_FVP_V2_1: 167 case REV_FOUNDATION_FVP_v9_1: 168 case REV_FOUNDATION_FVP_v9_6: 169 break; 170 default: 171 WARN("Unrecognized Foundation FVP revision %x\n", rev); 172 break; 173 } 174 break; 175 case HBI_BASE_FVP: 176 arm_config.flags |= ARM_CONFIG_BASE_MMAP | 177 ARM_CONFIG_HAS_INTERCONNECT | ARM_CONFIG_HAS_TZC; 178 179 /* 180 * Check for supported revisions 181 * Allow future revisions to run but emit warning diagnostic 182 */ 183 switch (rev) { 184 case REV_BASE_FVP_V0: 185 break; 186 default: 187 WARN("Unrecognized Base FVP revision %x\n", rev); 188 break; 189 } 190 break; 191 default: 192 ERROR("Unsupported board HBI number 0x%x\n", hbi); 193 panic(); 194 } 195 } 196 197 198 void fvp_interconnect_init(void) 199 { 200 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) { 201 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 202 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 203 ERROR("Unrecognized CCN variant detected. Only CCN-502" 204 " is supported"); 205 panic(); 206 } 207 #endif 208 plat_arm_interconnect_init(); 209 } 210 } 211 212 void fvp_interconnect_enable(void) 213 { 214 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 215 plat_arm_interconnect_enter_coherency(); 216 } 217 218 void fvp_interconnect_disable(void) 219 { 220 if (arm_config.flags & ARM_CONFIG_HAS_INTERCONNECT) 221 plat_arm_interconnect_exit_coherency(); 222 } 223