1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GIC_COMMON_H__ 8 #define __GIC_COMMON_H__ 9 10 /******************************************************************************* 11 * GIC Distributor interface general definitions 12 ******************************************************************************/ 13 /* Constants to categorise interrupts */ 14 #define MIN_SGI_ID 0 15 #define MIN_PPI_ID 16 16 #define MIN_SPI_ID 32 17 18 /* Mask for the priority field common to all GIC interfaces */ 19 #define GIC_PRI_MASK 0xff 20 21 /* Constant to indicate a spurious interrupt in all GIC versions */ 22 #define GIC_SPURIOUS_INTERRUPT 1023 23 24 /* Constants to categorise priorities */ 25 #define GIC_HIGHEST_SEC_PRIORITY 0 26 #define GIC_LOWEST_SEC_PRIORITY 127 27 #define GIC_HIGHEST_NS_PRIORITY 128 28 #define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */ 29 30 /******************************************************************************* 31 * GIC Distributor interface register offsets that are common to GICv3 & GICv2 32 ******************************************************************************/ 33 #define GICD_CTLR 0x0 34 #define GICD_TYPER 0x4 35 #define GICD_IIDR 0x8 36 #define GICD_IGROUPR 0x80 37 #define GICD_ISENABLER 0x100 38 #define GICD_ICENABLER 0x180 39 #define GICD_ISPENDR 0x200 40 #define GICD_ICPENDR 0x280 41 #define GICD_ISACTIVER 0x300 42 #define GICD_ICACTIVER 0x380 43 #define GICD_IPRIORITYR 0x400 44 #define GICD_ICFGR 0xc00 45 #define GICD_NSACR 0xe00 46 47 /* GICD_CTLR bit definitions */ 48 #define CTLR_ENABLE_G0_SHIFT 0 49 #define CTLR_ENABLE_G0_MASK 0x1 50 #define CTLR_ENABLE_G0_BIT (1 << CTLR_ENABLE_G0_SHIFT) 51 52 53 /******************************************************************************* 54 * GIC Distributor interface register constants that are common to GICv3 & GICv2 55 ******************************************************************************/ 56 #define PIDR2_ARCH_REV_SHIFT 4 57 #define PIDR2_ARCH_REV_MASK 0xf 58 59 /* GICv3 revision as reported by the PIDR2 register */ 60 #define ARCH_REV_GICV3 0x3 61 /* GICv2 revision as reported by the PIDR2 register */ 62 #define ARCH_REV_GICV2 0x2 63 64 #define IGROUPR_SHIFT 5 65 #define ISENABLER_SHIFT 5 66 #define ICENABLER_SHIFT ISENABLER_SHIFT 67 #define ISPENDR_SHIFT 5 68 #define ICPENDR_SHIFT ISPENDR_SHIFT 69 #define ISACTIVER_SHIFT 5 70 #define ICACTIVER_SHIFT ISACTIVER_SHIFT 71 #define IPRIORITYR_SHIFT 2 72 #define ICFGR_SHIFT 4 73 #define NSACR_SHIFT 4 74 75 /* GICD_TYPER shifts and masks */ 76 #define TYPER_IT_LINES_NO_SHIFT 0 77 #define TYPER_IT_LINES_NO_MASK 0x1f 78 79 /* Value used to initialize Normal world interrupt priorities four at a time */ 80 #define GICD_IPRIORITYR_DEF_VAL \ 81 (GIC_HIGHEST_NS_PRIORITY | \ 82 (GIC_HIGHEST_NS_PRIORITY << 8) | \ 83 (GIC_HIGHEST_NS_PRIORITY << 16) | \ 84 (GIC_HIGHEST_NS_PRIORITY << 24)) 85 86 #endif /* __GIC_COMMON_H__ */ 87