1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A72_H__ 8 #define __CORTEX_A72_H__ 9 10 /* Cortex-A72 midr for revision 0 */ 11 #define CORTEX_A72_MIDR 0x410FD080 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CPUECTLR p15, 1, c15 /* Instruction def. */ 17 18 #define CPUECTLR_SMP_BIT (1 << 6) 19 #define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT (1 << 38) 20 #define CPUECTLR_L2_IPFTCH_DIST_MASK (0x3 << 35) 21 #define CPUECTLR_L2_DPFTCH_DIST_MASK (0x3 << 32) 22 23 /******************************************************************************* 24 * CPU Memory Error Syndrome register specific definitions. 25 ******************************************************************************/ 26 #define CPUMERRSR p15, 2, c15 /* Instruction def. */ 27 28 /******************************************************************************* 29 * CPU Auxiliary Control register specific definitions. 30 ******************************************************************************/ 31 #define CPUACTLR p15, 0, c15 /* Instruction def. */ 32 33 #define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) 34 #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) 35 #define CPUACTLR_DCC_AS_DCCI (1 << 44) 36 37 /******************************************************************************* 38 * L2 Control register specific definitions. 39 ******************************************************************************/ 40 #define L2CTLR p15, 1, c9, c0, 3 /* Instruction def. */ 41 42 #define L2CTLR_DATA_RAM_LATENCY_SHIFT 0 43 #define L2CTLR_TAG_RAM_LATENCY_SHIFT 6 44 45 #define L2_DATA_RAM_LATENCY_3_CYCLES 0x2 46 #define L2_TAG_RAM_LATENCY_2_CYCLES 0x1 47 #define L2_TAG_RAM_LATENCY_3_CYCLES 0x2 48 49 /******************************************************************************* 50 * L2 Memory Error Syndrome register specific definitions. 51 ******************************************************************************/ 52 #define L2MERRSR p15, 3, c15 /* Instruction def. */ 53 54 #endif /* __CORTEX_A72_H__ */ 55