1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __FVP_DEF_H__ 8 #define __FVP_DEF_H__ 9 10 #include <arm_def.h> 11 12 #ifndef FVP_CLUSTER_COUNT 13 #define FVP_CLUSTER_COUNT 2 14 #endif 15 #define FVP_MAX_CPUS_PER_CLUSTER 4 16 17 #define FVP_PRIMARY_CPU 0x0 18 19 /* Defines for the Interconnect build selection */ 20 #define FVP_CCI 1 21 #define FVP_CCN 2 22 23 /******************************************************************************* 24 * FVP memory map related constants 25 ******************************************************************************/ 26 27 #define FLASH1_BASE 0x0c000000 28 #define FLASH1_SIZE 0x04000000 29 30 #define PSRAM_BASE 0x14000000 31 #define PSRAM_SIZE 0x04000000 32 33 #define VRAM_BASE 0x18000000 34 #define VRAM_SIZE 0x02000000 35 36 /* Aggregate of all devices in the first GB */ 37 #define DEVICE0_BASE 0x20000000 38 #define DEVICE0_SIZE 0x0c200000 39 40 /* 41 * In case of FVP models with CCN, the CCN register space overlaps into 42 * the NSRAM area. 43 */ 44 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 45 #define DEVICE1_BASE 0x2e000000 46 #define DEVICE1_SIZE 0x1A00000 47 #else 48 #define DEVICE1_BASE 0x2f000000 49 #define DEVICE1_SIZE 0x200000 50 #define NSRAM_BASE 0x2e000000 51 #define NSRAM_SIZE 0x10000 52 #endif 53 /* Devices in the second GB */ 54 #define DEVICE2_BASE 0x7fe00000 55 #define DEVICE2_SIZE 0x00200000 56 57 #define PCIE_EXP_BASE 0x40000000 58 #define TZRNG_BASE 0x7fe60000 59 60 /* Non-volatile counters */ 61 #define TRUSTED_NVCTR_BASE 0x7fe70000 62 #define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000) 63 #define TFW_NVCTR_SIZE 4 64 #define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004) 65 #define NTFW_CTR_SIZE 4 66 67 /* Keys */ 68 #define SOC_KEYS_BASE 0x7fe80000 69 #define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000) 70 #define TZ_PUB_KEY_HASH_SIZE 32 71 #define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020) 72 #define HU_KEY_SIZE 16 73 #define END_KEY_BASE (SOC_KEYS_BASE + 0x0044) 74 #define END_KEY_SIZE 32 75 76 /* Constants to distinguish FVP type */ 77 #define HBI_BASE_FVP 0x020 78 #define REV_BASE_FVP_V0 0x0 79 80 #define HBI_FOUNDATION_FVP 0x010 81 #define REV_FOUNDATION_FVP_V2_0 0x0 82 #define REV_FOUNDATION_FVP_V2_1 0x1 83 #define REV_FOUNDATION_FVP_v9_1 0x2 84 #define REV_FOUNDATION_FVP_v9_6 0x3 85 86 #define BLD_GIC_VE_MMAP 0x0 87 #define BLD_GIC_A53A57_MMAP 0x1 88 89 #define ARCH_MODEL 0x1 90 91 /* FVP Power controller base address*/ 92 #define PWRC_BASE 0x1c100000 93 94 /* FVP SP804 timer frequency is 35 MHz*/ 95 #define SP804_TIMER_CLKMULT 1 96 #define SP804_TIMER_CLKDIV 35 97 98 /* SP810 controller. FVP specific flags */ 99 #define FVP_SP810_CTRL_TIM0_OV (1 << 16) 100 #define FVP_SP810_CTRL_TIM1_OV (1 << 18) 101 #define FVP_SP810_CTRL_TIM2_OV (1 << 20) 102 #define FVP_SP810_CTRL_TIM3_OV (1 << 22) 103 104 /******************************************************************************* 105 * GIC-400 & interrupt handling related constants 106 ******************************************************************************/ 107 /* VE compatible GIC memory map */ 108 #define VE_GICD_BASE 0x2c001000 109 #define VE_GICC_BASE 0x2c002000 110 #define VE_GICH_BASE 0x2c004000 111 #define VE_GICV_BASE 0x2c006000 112 113 /* Base FVP compatible GIC memory map */ 114 #define BASE_GICD_BASE 0x2f000000 115 #define BASE_GICR_BASE 0x2f100000 116 #define BASE_GICC_BASE 0x2c000000 117 #define BASE_GICH_BASE 0x2c010000 118 #define BASE_GICV_BASE 0x2c02f000 119 120 #define FVP_IRQ_TZ_WDOG 56 121 #define FVP_IRQ_SEC_SYS_TIMER 57 122 123 124 /******************************************************************************* 125 * TrustZone address space controller related constants 126 ******************************************************************************/ 127 128 /* NSAIDs used by devices in TZC filter 0 on FVP */ 129 #define FVP_NSAID_DEFAULT 0 130 #define FVP_NSAID_PCI 1 131 #define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */ 132 #define FVP_NSAID_AP 9 /* Application Processors */ 133 #define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */ 134 135 /* NSAIDs used by devices in TZC filter 2 on FVP */ 136 #define FVP_NSAID_HDLCD0 2 137 #define FVP_NSAID_CLCD 7 138 139 #endif /* __FVP_DEF_H__ */ 140