1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <platform_def.h> 10 11 #include <arch.h> 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/pl011.h> 16 #include <lib/mmio.h> 17 18 #include <sq_common.h> 19 20 static console_pl011_t console; 21 static entry_point_info_t bl32_image_ep_info; 22 static entry_point_info_t bl33_image_ep_info; 23 24 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 25 { 26 assert(sec_state_is_valid(type)); 27 return type == NON_SECURE ? &bl33_image_ep_info : &bl32_image_ep_info; 28 } 29 30 /******************************************************************************* 31 * Gets SPSR for BL32 entry 32 ******************************************************************************/ 33 uint32_t sq_get_spsr_for_bl32_entry(void) 34 { 35 /* 36 * The Secure Payload Dispatcher service is responsible for 37 * setting the SPSR prior to entry into the BL32 image. 38 */ 39 return 0; 40 } 41 42 /******************************************************************************* 43 * Gets SPSR for BL33 entry 44 ******************************************************************************/ 45 uint32_t sq_get_spsr_for_bl33_entry(void) 46 { 47 unsigned long el_status; 48 unsigned int mode; 49 uint32_t spsr; 50 51 /* Figure out what mode we enter the non-secure world in */ 52 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 53 el_status &= ID_AA64PFR0_ELX_MASK; 54 55 mode = (el_status) ? MODE_EL2 : MODE_EL1; 56 57 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 58 return spsr; 59 } 60 61 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 62 u_register_t arg2, u_register_t arg3) 63 { 64 /* Initialize the console to provide early debug support */ 65 (void)console_pl011_register(PLAT_SQ_BOOT_UART_BASE, 66 PLAT_SQ_BOOT_UART_CLK_IN_HZ, 67 SQ_CONSOLE_BAUDRATE, &console); 68 69 console_set_scope(&console.console, CONSOLE_FLAG_BOOT | 70 CONSOLE_FLAG_RUNTIME); 71 72 /* There are no parameters from BL2 if BL31 is a reset vector */ 73 assert(arg0 == 0U); 74 assert(arg1 == 0U); 75 76 /* Initialize power controller before setting up topology */ 77 plat_sq_pwrc_setup(); 78 79 #ifdef BL32_BASE 80 struct draminfo di = {0}; 81 82 scpi_get_draminfo(&di); 83 84 /* 85 * Check if OP-TEE has been loaded in Secure RAM allocated 86 * from DRAM1 region 87 */ 88 if ((di.base1 + di.size1) <= BL32_BASE) { 89 NOTICE("OP-TEE has been loaded by SCP firmware\n"); 90 /* Populate entry point information for BL32 */ 91 SET_PARAM_HEAD(&bl32_image_ep_info, 92 PARAM_EP, 93 VERSION_1, 94 0); 95 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 96 bl32_image_ep_info.pc = BL32_BASE; 97 bl32_image_ep_info.spsr = sq_get_spsr_for_bl32_entry(); 98 } else { 99 NOTICE("OP-TEE has not been loaded by SCP firmware\n"); 100 } 101 #endif /* BL32_BASE */ 102 103 /* Populate entry point information for BL33 */ 104 SET_PARAM_HEAD(&bl33_image_ep_info, 105 PARAM_EP, 106 VERSION_1, 107 0); 108 /* 109 * Tell BL31 where the non-trusted software image 110 * is located and the entry state information 111 */ 112 bl33_image_ep_info.pc = PRELOADED_BL33_BASE; 113 bl33_image_ep_info.spsr = sq_get_spsr_for_bl33_entry(); 114 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 115 } 116 117 static void sq_configure_sys_timer(void) 118 { 119 unsigned int reg_val; 120 121 reg_val = (1 << CNTACR_RPCT_SHIFT) | (1 << CNTACR_RVCT_SHIFT); 122 reg_val |= (1 << CNTACR_RFRQ_SHIFT) | (1 << CNTACR_RVOFF_SHIFT); 123 reg_val |= (1 << CNTACR_RWVT_SHIFT) | (1 << CNTACR_RWPT_SHIFT); 124 mmio_write_32(SQ_SYS_TIMCTL_BASE + 125 CNTACR_BASE(PLAT_SQ_NSTIMER_FRAME_ID), reg_val); 126 127 reg_val = (1 << CNTNSAR_NS_SHIFT(PLAT_SQ_NSTIMER_FRAME_ID)); 128 mmio_write_32(SQ_SYS_TIMCTL_BASE + CNTNSAR, reg_val); 129 } 130 131 void bl31_platform_setup(void) 132 { 133 /* Initialize the CCN interconnect */ 134 plat_sq_interconnect_init(); 135 plat_sq_interconnect_enter_coherency(); 136 137 /* Initialize the GIC driver, cpu and distributor interfaces */ 138 sq_gic_driver_init(); 139 sq_gic_init(); 140 141 /* Enable and initialize the System level generic timer */ 142 mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, 143 CNTCR_FCREQ(0U) | CNTCR_EN); 144 145 /* Allow access to the System counter timer module */ 146 sq_configure_sys_timer(); 147 } 148 149 void bl31_plat_runtime_setup(void) 150 { 151 struct draminfo *di = (struct draminfo *)(unsigned long)DRAMINFO_BASE; 152 153 scpi_get_draminfo(di); 154 } 155 156 void bl31_plat_arch_setup(void) 157 { 158 sq_mmap_setup(BL31_BASE, BL31_SIZE, NULL); 159 enable_mmu_el3(XLAT_TABLE_NC); 160 } 161 162 void bl31_plat_enable_mmu(uint32_t flags) 163 { 164 enable_mmu_el3(flags | XLAT_TABLE_NC); 165 } 166 167 unsigned int plat_get_syscnt_freq2(void) 168 { 169 unsigned int counter_base_frequency; 170 171 /* Read the frequency from Frequency modes table */ 172 counter_base_frequency = mmio_read_32(SQ_SYS_CNTCTL_BASE + CNTFID_OFF); 173 174 /* The first entry of the frequency modes table must not be 0 */ 175 if (counter_base_frequency == 0) 176 panic(); 177 178 return counter_base_frequency; 179 } 180