1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <debug.h> 8 #include <platform_def.h> 9 #include <xlat_tables_v2.h> 10 11 #define SQ_REG_REGION_BASE 0x20000000ULL 12 #define SQ_REG_REGION_SIZE 0x60000000ULL 13 14 void sq_mmap_setup(uintptr_t total_base, size_t total_size, 15 const struct mmap_region *mmap) 16 { 17 VERBOSE("Trusted RAM seen by this BL image: %p - %p\n", 18 (void *)total_base, (void *)(total_base + total_size)); 19 mmap_add_region(total_base, total_base, 20 total_size, 21 MT_NON_CACHEABLE | MT_RW | MT_SECURE); 22 23 /* remap the code section */ 24 VERBOSE("Code region: %p - %p\n", 25 (void *)BL_CODE_BASE, (void *)BL_CODE_END); 26 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 27 round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE, 28 MT_NON_CACHEABLE | MT_RO | MT_SECURE); 29 30 /* Re-map the read-only data section */ 31 VERBOSE("Read-only data region: %p - %p\n", 32 (void *)BL_RO_DATA_BASE, (void *)BL_RO_DATA_END); 33 mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, 34 round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE, 35 (MT_NON_CACHEABLE | MT_RO | MT_EXECUTE_NEVER | 36 MT_SECURE)); 37 38 /* remap the coherent memory region */ 39 VERBOSE("Coherent region: %p - %p\n", 40 (void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END); 41 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, 42 BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, 43 MT_DEVICE | MT_RW | MT_SECURE); 44 45 /* register region */ 46 mmap_add_region(SQ_REG_REGION_BASE, SQ_REG_REGION_BASE, 47 SQ_REG_REGION_SIZE, 48 MT_DEVICE | MT_RW | MT_SECURE); 49 50 /* additional regions if needed */ 51 if (mmap) 52 mmap_add(mmap); 53 54 init_xlat_tables(); 55 } 56