1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <context.h> 16 #include <drivers/arm/cci.h> 17 #include <drivers/console.h> 18 #include <lib/el3_runtime/context_mgmt.h> 19 #include <lib/mmio.h> 20 #include <lib/xlat_tables/xlat_tables.h> 21 #include <plat/common/platform.h> 22 23 #include <imx8qx_pads.h> 24 #include <imx8_iomux.h> 25 #include <imx8_lpuart.h> 26 #include <plat_imx8.h> 27 #include <sci/sci.h> 28 #include <sec_rsrc.h> 29 30 IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START); 31 IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END); 32 IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_START); 33 IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_END); 34 IMPORT_SYM(unsigned long, __RW_START__, BL31_RW_START); 35 IMPORT_SYM(unsigned long, __RW_END__, BL31_RW_END); 36 37 static entry_point_info_t bl32_image_ep_info; 38 static entry_point_info_t bl33_image_ep_info; 39 40 #define UART_PAD_CTRL (PADRING_IFMUX_EN_MASK | PADRING_GP_EN_MASK | \ 41 (SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \ 42 (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \ 43 (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \ 44 (SC_PAD_28FDSOI_PS_PD << PADRING_PULL_SHIFT)) 45 46 static const mmap_region_t imx_mmap[] = { 47 MAP_REGION_FLAT(IMX_BOOT_UART_BASE, IMX_BOOT_UART_SIZE, MT_DEVICE | MT_RW), 48 MAP_REGION_FLAT(SC_IPC_BASE, SC_IPC_SIZE, MT_DEVICE | MT_RW), 49 MAP_REGION_FLAT(PLAT_GICD_BASE, PLAT_GICD_SIZE, MT_DEVICE | MT_RW), 50 MAP_REGION_FLAT(PLAT_GICR_BASE, PLAT_GICR_SIZE, MT_DEVICE | MT_RW), 51 {0} 52 }; 53 54 static uint32_t get_spsr_for_bl33_entry(void) 55 { 56 unsigned long el_status; 57 unsigned long mode; 58 uint32_t spsr; 59 60 /* figure out what mode we enter the non-secure world */ 61 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 62 el_status &= ID_AA64PFR0_ELX_MASK; 63 64 mode = (el_status) ? MODE_EL2 : MODE_EL1; 65 66 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 67 return spsr; 68 } 69 70 #if DEBUG_CONSOLE_A35 71 static void lpuart32_serial_setbrg(unsigned int base, int baudrate) 72 { 73 unsigned int sbr, osr, baud_diff, tmp_osr, tmp_sbr; 74 unsigned int diff1, diff2, tmp, rate; 75 76 if (baudrate == 0) 77 panic(); 78 79 sc_pm_get_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 80 81 baud_diff = baudrate; 82 osr = 0; 83 sbr = 0; 84 for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) { 85 tmp_sbr = (rate / (baudrate * tmp_osr)); 86 if (tmp_sbr == 0) 87 tmp_sbr = 1; 88 89 /* calculate difference in actual baud w/ current values */ 90 diff1 = rate / (tmp_osr * tmp_sbr) - baudrate; 91 diff2 = rate / (tmp_osr * (tmp_sbr + 1)); 92 93 /* select best values between sbr and sbr+1 */ 94 if (diff1 > (baudrate - diff2)) { 95 diff1 = baudrate - diff2; 96 tmp_sbr++; 97 } 98 99 if (diff1 <= baud_diff) { 100 baud_diff = diff1; 101 osr = tmp_osr; 102 sbr = tmp_sbr; 103 } 104 } 105 106 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); 107 108 if ((osr > 3) && (osr < 8)) 109 tmp |= LPUART_BAUD_BOTHEDGE_MASK; 110 111 tmp &= ~LPUART_BAUD_OSR_MASK; 112 tmp |= LPUART_BAUD_OSR(osr - 1); 113 tmp &= ~LPUART_BAUD_SBR_MASK; 114 tmp |= LPUART_BAUD_SBR(sbr); 115 116 /* explicitly disable 10 bit mode & set 1 stop bit */ 117 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); 118 119 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); 120 } 121 122 static int lpuart32_serial_init(unsigned int base) 123 { 124 unsigned int tmp; 125 126 /* disable TX & RX before enabling clocks */ 127 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 128 tmp &= ~(CTRL_TE | CTRL_RE); 129 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 130 131 mmio_write_32(IMX_BOOT_UART_BASE + MODIR, 0); 132 mmio_write_32(IMX_BOOT_UART_BASE + FIFO, ~(FIFO_TXFE | FIFO_RXFE)); 133 134 mmio_write_32(IMX_BOOT_UART_BASE + MATCH, 0); 135 136 /* provide data bits, parity, stop bit, etc */ 137 lpuart32_serial_setbrg(base, IMX_BOOT_UART_BAUDRATE); 138 139 /* eight data bits no parity bit */ 140 tmp = mmio_read_32(IMX_BOOT_UART_BASE + CTRL); 141 tmp &= ~(LPUART_CTRL_PE_MASK | LPUART_CTRL_PT_MASK | LPUART_CTRL_M_MASK); 142 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, tmp); 143 144 mmio_write_32(IMX_BOOT_UART_BASE + CTRL, CTRL_RE | CTRL_TE); 145 146 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 147 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x55); 148 mmio_write_32(IMX_BOOT_UART_BASE + DATA, 0x0A); 149 150 return 0; 151 } 152 #endif 153 154 void imx8_partition_resources(void) 155 { 156 sc_rm_pt_t secure_part, os_part; 157 sc_rm_mr_t mr, mr_record = 64; 158 sc_faddr_t start, end; 159 sc_err_t err; 160 bool owned; 161 int i; 162 163 err = sc_rm_get_partition(ipc_handle, &secure_part); 164 if (err) 165 ERROR("sc_rm_get_partition failed: %u\n", err); 166 167 err = sc_rm_partition_alloc(ipc_handle, &os_part, false, false, 168 false, false, false); 169 if (err) 170 ERROR("sc_rm_partition_alloc failed: %u\n", err); 171 172 err = sc_rm_set_parent(ipc_handle, os_part, secure_part); 173 if (err) 174 ERROR("sc_rm_set_parent: %u\n", err); 175 176 /* set secure resources to NOT-movable */ 177 for (i = 0; i < (ARRAY_SIZE(secure_rsrcs)); i++) { 178 err = sc_rm_set_resource_movable(ipc_handle, 179 secure_rsrcs[i], secure_rsrcs[i], false); 180 if (err) 181 ERROR("sc_rm_set_resource_movable: rsrc %u, ret %u\n", 182 secure_rsrcs[i], err); 183 } 184 185 /* move all movable resources and pins to non-secure partition */ 186 err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true); 187 if (err) 188 ERROR("sc_rm_move_all: %u\n", err); 189 190 /* iterate through peripherals to give NS OS part access */ 191 for (i = 0; i < ARRAY_SIZE(ns_access_allowed); i++) { 192 err = sc_rm_set_peripheral_permissions(ipc_handle, 193 ns_access_allowed[i], os_part, SC_RM_PERM_FULL); 194 if (err) 195 ERROR("sc_rm_set_peripheral_permissions: rsrc %u, \ 196 ret %u\n", ns_access_allowed[i], err); 197 } 198 199 /* 200 * sc_rm_set_peripheral_permissions 201 * sc_rm_set_memreg_permissions 202 * sc_rm_set_pin_movable 203 */ 204 for (mr = 0; mr < 64; mr++) { 205 owned = sc_rm_is_memreg_owned(ipc_handle, mr); 206 if (owned) { 207 err = sc_rm_get_memreg_info(ipc_handle, mr, &start, &end); 208 if (err) 209 ERROR("Memreg get info failed, %u\n", mr); 210 211 NOTICE("Memreg %u 0x%llx -- 0x%llx\n", mr, start, end); 212 if (BL31_BASE >= start && (BL31_LIMIT - 1) <= end) { 213 mr_record = mr; /* Record the mr for ATF running */ 214 } else { 215 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 216 if (err) 217 ERROR("Memreg assign failed, 0x%llx -- 0x%llx, \ 218 err %d\n", start, end, err); 219 } 220 } 221 } 222 223 if (mr_record != 64) { 224 err = sc_rm_get_memreg_info(ipc_handle, mr_record, &start, &end); 225 if (err) 226 ERROR("Memreg get info failed, %u\n", mr_record); 227 if ((BL31_LIMIT - 1) < end) { 228 err = sc_rm_memreg_alloc(ipc_handle, &mr, BL31_LIMIT, end); 229 if (err) 230 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 231 (sc_faddr_t)BL31_LIMIT, end); 232 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 233 if (err) 234 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 235 (sc_faddr_t)BL31_LIMIT, end); 236 } 237 238 if (start < (BL31_BASE - 1)) { 239 err = sc_rm_memreg_alloc(ipc_handle, &mr, start, BL31_BASE - 1); 240 if (err) 241 ERROR("sc_rm_memreg_alloc failed, 0x%llx -- 0x%llx\n", 242 start, (sc_faddr_t)BL31_BASE - 1); 243 err = sc_rm_assign_memreg(ipc_handle, os_part, mr); 244 if (err) 245 ERROR("Memreg assign failed, 0x%llx -- 0x%llx\n", 246 start, (sc_faddr_t)BL31_BASE - 1); 247 } 248 } 249 250 if (err) 251 NOTICE("Partitioning Failed\n"); 252 else 253 NOTICE("Non-secure Partitioning Succeeded\n"); 254 } 255 256 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 257 u_register_t arg2, u_register_t arg3) 258 { 259 #if DEBUG_CONSOLE 260 static console_lpuart_t console; 261 #endif 262 if (sc_ipc_open(&ipc_handle, SC_IPC_BASE) != SC_ERR_NONE) 263 panic(); 264 265 #if DEBUG_CONSOLE_A35 266 sc_pm_set_resource_power_mode(ipc_handle, SC_R_UART_0, SC_PM_PW_MODE_ON); 267 sc_pm_clock_rate_t rate = 80000000; 268 sc_pm_set_clock_rate(ipc_handle, SC_R_UART_0, 2, &rate); 269 sc_pm_clock_enable(ipc_handle, SC_R_UART_0, 2, true, false); 270 271 /* Configure UART pads */ 272 sc_pad_set(ipc_handle, SC_P_UART0_RX, UART_PAD_CTRL); 273 sc_pad_set(ipc_handle, SC_P_UART0_TX, UART_PAD_CTRL); 274 lpuart32_serial_init(IMX_BOOT_UART_BASE); 275 #endif 276 277 #if DEBUG_CONSOLE 278 console_lpuart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 279 IMX_CONSOLE_BAUDRATE, &console); 280 #endif 281 /* Turn on MU1 for non-secure OS/Hypervisor */ 282 sc_pm_set_resource_power_mode(ipc_handle, SC_R_MU_1A, SC_PM_PW_MODE_ON); 283 284 /* 285 * create new partition for non-secure OS/Hypervisor 286 * uses global structs defined in sec_rsrc.h 287 */ 288 imx8_partition_resources(); 289 290 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 291 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry(); 292 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 293 } 294 295 void bl31_plat_arch_setup(void) 296 { 297 unsigned long ro_start = BL31_RO_START; 298 unsigned long ro_size = BL31_RO_END - BL31_RO_START; 299 unsigned long rw_start = BL31_RW_START; 300 unsigned long rw_size = BL31_RW_END - BL31_RW_START; 301 #if USE_COHERENT_MEM 302 unsigned long coh_start = BL31_COHERENT_RAM_START; 303 unsigned long coh_size = BL31_COHERENT_RAM_END - BL31_COHERENT_RAM_START; 304 #endif 305 306 mmap_add_region(ro_start, ro_start, ro_size, 307 MT_RO | MT_MEMORY | MT_SECURE); 308 mmap_add_region(rw_start, rw_start, rw_size, 309 MT_RW | MT_MEMORY | MT_SECURE); 310 mmap_add(imx_mmap); 311 312 #if USE_COHERENT_MEM 313 mmap_add_region(coh_start, coh_start, coh_size, 314 MT_DEVICE | MT_RW | MT_SECURE); 315 #endif 316 317 init_xlat_tables(); 318 enable_mmu_el3(0); 319 } 320 321 void bl31_platform_setup(void) 322 { 323 plat_gic_driver_init(); 324 plat_gic_init(); 325 } 326 327 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 328 { 329 if (type == NON_SECURE) 330 return &bl33_image_ep_info; 331 if (type == SECURE) 332 return &bl32_image_ep_info; 333 334 return NULL; 335 } 336 337 unsigned int plat_get_syscnt_freq2(void) 338 { 339 return COUNTER_FREQUENCY; 340 } 341 342 void bl31_plat_runtime_setup(void) 343 { 344 return; 345 } 346