1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <lib/psci/psci.h> 14 #include <plat/common/platform.h> 15 16 #include <arm_def.h> 17 #include <plat_arm.h> 18 19 /* Allow ARM Standard platforms to override these functions */ 20 #pragma weak plat_arm_program_trusted_mailbox 21 22 #if !ARM_RECOM_STATE_ID_ENC 23 /******************************************************************************* 24 * ARM standard platform handler called to check the validity of the power state 25 * parameter. 26 ******************************************************************************/ 27 int arm_validate_power_state(unsigned int power_state, 28 psci_power_state_t *req_state) 29 { 30 unsigned int pstate = psci_get_pstate_type(power_state); 31 unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 32 unsigned int i; 33 34 assert(req_state != NULL); 35 36 if (pwr_lvl > PLAT_MAX_PWR_LVL) 37 return PSCI_E_INVALID_PARAMS; 38 39 /* Sanity check the requested state */ 40 if (pstate == PSTATE_TYPE_STANDBY) { 41 /* 42 * It's possible to enter standby only on power level 0 43 * Ignore any other power level. 44 */ 45 if (pwr_lvl != ARM_PWR_LVL0) 46 return PSCI_E_INVALID_PARAMS; 47 48 req_state->pwr_domain_state[ARM_PWR_LVL0] = 49 ARM_LOCAL_STATE_RET; 50 } else { 51 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 52 req_state->pwr_domain_state[i] = 53 ARM_LOCAL_STATE_OFF; 54 } 55 56 /* 57 * We expect the 'state id' to be zero. 58 */ 59 if (psci_get_pstate_id(power_state) != 0U) 60 return PSCI_E_INVALID_PARAMS; 61 62 return PSCI_E_SUCCESS; 63 } 64 65 #else 66 /******************************************************************************* 67 * ARM standard platform handler called to check the validity of the power 68 * state parameter. The power state parameter has to be a composite power 69 * state. 70 ******************************************************************************/ 71 int arm_validate_power_state(unsigned int power_state, 72 psci_power_state_t *req_state) 73 { 74 unsigned int state_id; 75 int i; 76 77 assert(req_state != NULL); 78 79 /* 80 * Currently we are using a linear search for finding the matching 81 * entry in the idle power state array. This can be made a binary 82 * search if the number of entries justify the additional complexity. 83 */ 84 for (i = 0; !!arm_pm_idle_states[i]; i++) { 85 if (power_state == arm_pm_idle_states[i]) 86 break; 87 } 88 89 /* Return error if entry not found in the idle state array */ 90 if (!arm_pm_idle_states[i]) 91 return PSCI_E_INVALID_PARAMS; 92 93 i = 0; 94 state_id = psci_get_pstate_id(power_state); 95 96 /* Parse the State ID and populate the state info parameter */ 97 while (state_id) { 98 req_state->pwr_domain_state[i++] = state_id & 99 ARM_LOCAL_PSTATE_MASK; 100 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 101 } 102 103 return PSCI_E_SUCCESS; 104 } 105 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 106 107 /******************************************************************************* 108 * ARM standard platform handler called to check the validity of the non secure 109 * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise. 110 ******************************************************************************/ 111 int arm_validate_ns_entrypoint(uintptr_t entrypoint) 112 { 113 /* 114 * Check if the non secure entrypoint lies within the non 115 * secure DRAM. 116 */ 117 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 118 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) { 119 return 0; 120 } 121 #ifndef AARCH32 122 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 123 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) { 124 return 0; 125 } 126 #endif 127 128 return -1; 129 } 130 131 int arm_validate_psci_entrypoint(uintptr_t entrypoint) 132 { 133 return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS : 134 PSCI_E_INVALID_ADDRESS; 135 } 136 137 /****************************************************************************** 138 * Helper function to save the platform state before a system suspend. Save the 139 * state of the system components which are not in the Always ON power domain. 140 *****************************************************************************/ 141 void arm_system_pwr_domain_save(void) 142 { 143 /* Assert system power domain is available on the platform */ 144 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 145 146 plat_arm_gic_save(); 147 148 /* 149 * Unregister console now so that it is not registered for a second 150 * time during resume. 151 */ 152 arm_console_runtime_end(); 153 154 /* 155 * All the other peripheral which are configured by ARM TF are 156 * re-initialized on resume from system suspend. Hence we 157 * don't save their state here. 158 */ 159 } 160 161 /****************************************************************************** 162 * Helper function to resume the platform from system suspend. Reinitialize 163 * the system components which are not in the Always ON power domain. 164 * TODO: Unify the platform setup when waking up from cold boot and system 165 * resume in arm_bl31_platform_setup(). 166 *****************************************************************************/ 167 void arm_system_pwr_domain_resume(void) 168 { 169 /* Initialize the console */ 170 arm_console_runtime_init(); 171 172 /* Assert system power domain is available on the platform */ 173 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 174 175 plat_arm_gic_resume(); 176 177 plat_arm_security_setup(); 178 arm_configure_sys_timer(); 179 } 180 181 /******************************************************************************* 182 * ARM platform function to program the mailbox for a cpu before it is released 183 * from reset. This function assumes that the Trusted mail box base is within 184 * the ARM_SHARED_RAM region 185 ******************************************************************************/ 186 void plat_arm_program_trusted_mailbox(uintptr_t address) 187 { 188 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 189 190 *mailbox = address; 191 192 /* 193 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 194 * ARM_SHARED_RAM region. 195 */ 196 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 197 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ 198 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 199 } 200 201 /******************************************************************************* 202 * The ARM Standard platform definition of platform porting API 203 * `plat_setup_psci_ops`. 204 ******************************************************************************/ 205 int __init plat_setup_psci_ops(uintptr_t sec_entrypoint, 206 const plat_psci_ops_t **psci_ops) 207 { 208 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 209 210 /* Setup mailbox with entry point. */ 211 plat_arm_program_trusted_mailbox(sec_entrypoint); 212 return 0; 213 } 214