1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A73_H__ 8 #define __CORTEX_A73_H__ 9 10 /* Cortex-A73 midr for revision 0 */ 11 #define CORTEX_A73_MIDR 0x410FD090 12 13 /******************************************************************************* 14 * CPU Extended Control register specific definitions. 15 ******************************************************************************/ 16 #define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */ 17 18 #define CORTEX_A73_CPUECTLR_SMP_BIT (1 << 6) 19 20 /******************************************************************************* 21 * L2 Memory Error Syndrome register specific definitions. 22 ******************************************************************************/ 23 #define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */ 24 25 #endif /* __CORTEX_A73_H__ */ 26