1/* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <platform_def.h> 8 9OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 10OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 11ENTRY(bl31_entrypoint) 12 13 14MEMORY { 15 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 16} 17 18#ifdef PLAT_EXTRA_LD_SCRIPT 19#include <plat.ld.S> 20#endif 21 22SECTIONS 23{ 24 . = BL31_BASE; 25 ASSERT(. == ALIGN(4096), 26 "BL31_BASE address is not aligned on a page boundary.") 27 28#if SEPARATE_CODE_AND_RODATA 29 .text . : { 30 __TEXT_START__ = .; 31 *bl31_entrypoint.o(.text*) 32 *(.text*) 33 *(.vectors) 34 . = NEXT(4096); 35 __TEXT_END__ = .; 36 } >RAM 37 38 .rodata . : { 39 __RODATA_START__ = .; 40 *(.rodata*) 41 42 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 43 . = ALIGN(8); 44 __RT_SVC_DESCS_START__ = .; 45 KEEP(*(rt_svc_descs)) 46 __RT_SVC_DESCS_END__ = .; 47 48#if ENABLE_PMF 49 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 50 . = ALIGN(8); 51 __PMF_SVC_DESCS_START__ = .; 52 KEEP(*(pmf_svc_descs)) 53 __PMF_SVC_DESCS_END__ = .; 54#endif /* ENABLE_PMF */ 55 56 /* 57 * Ensure 8-byte alignment for cpu_ops so that its fields are also 58 * aligned. Also ensure cpu_ops inclusion. 59 */ 60 . = ALIGN(8); 61 __CPU_OPS_START__ = .; 62 KEEP(*(cpu_ops)) 63 __CPU_OPS_END__ = .; 64 65 . = NEXT(4096); 66 __RODATA_END__ = .; 67 } >RAM 68#else 69 ro . : { 70 __RO_START__ = .; 71 *bl31_entrypoint.o(.text*) 72 *(.text*) 73 *(.rodata*) 74 75 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 76 . = ALIGN(8); 77 __RT_SVC_DESCS_START__ = .; 78 KEEP(*(rt_svc_descs)) 79 __RT_SVC_DESCS_END__ = .; 80 81#if ENABLE_PMF 82 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 83 . = ALIGN(8); 84 __PMF_SVC_DESCS_START__ = .; 85 KEEP(*(pmf_svc_descs)) 86 __PMF_SVC_DESCS_END__ = .; 87#endif /* ENABLE_PMF */ 88 89 /* 90 * Ensure 8-byte alignment for cpu_ops so that its fields are also 91 * aligned. Also ensure cpu_ops inclusion. 92 */ 93 . = ALIGN(8); 94 __CPU_OPS_START__ = .; 95 KEEP(*(cpu_ops)) 96 __CPU_OPS_END__ = .; 97 98 *(.vectors) 99 __RO_END_UNALIGNED__ = .; 100 /* 101 * Memory page(s) mapped to this section will be marked as read-only, 102 * executable. No RW data from the next section must creep in. 103 * Ensure the rest of the current memory page is unused. 104 */ 105 . = NEXT(4096); 106 __RO_END__ = .; 107 } >RAM 108#endif 109 110 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 111 "cpu_ops not defined for this platform.") 112 113 /* 114 * Define a linker symbol to mark start of the RW memory area for this 115 * image. 116 */ 117 __RW_START__ = . ; 118 119 /* 120 * .data must be placed at a lower address than the stacks if the stack 121 * protector is enabled. Alternatively, the .data.stack_protector_canary 122 * section can be placed independently of the main .data section. 123 */ 124 .data . : { 125 __DATA_START__ = .; 126 *(.data*) 127 __DATA_END__ = .; 128 } >RAM 129 130#ifdef BL31_PROGBITS_LIMIT 131 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 132#endif 133 134 stacks (NOLOAD) : { 135 __STACKS_START__ = .; 136 *(tzfw_normal_stacks) 137 __STACKS_END__ = .; 138 } >RAM 139 140 /* 141 * The .bss section gets initialised to 0 at runtime. 142 * Its base address should be 16-byte aligned for better performance of the 143 * zero-initialization code. 144 */ 145 .bss (NOLOAD) : ALIGN(16) { 146 __BSS_START__ = .; 147 *(.bss*) 148 *(COMMON) 149#if !USE_COHERENT_MEM 150 /* 151 * Bakery locks are stored in normal .bss memory 152 * 153 * Each lock's data is spread across multiple cache lines, one per CPU, 154 * but multiple locks can share the same cache line. 155 * The compiler will allocate enough memory for one CPU's bakery locks, 156 * the remaining cache lines are allocated by the linker script 157 */ 158 . = ALIGN(CACHE_WRITEBACK_GRANULE); 159 __BAKERY_LOCK_START__ = .; 160 *(bakery_lock) 161 . = ALIGN(CACHE_WRITEBACK_GRANULE); 162 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 163 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 164 __BAKERY_LOCK_END__ = .; 165#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 166 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 167 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 168#endif 169#endif 170 171#if ENABLE_PMF 172 /* 173 * Time-stamps are stored in normal .bss memory 174 * 175 * The compiler will allocate enough memory for one CPU's time-stamps, 176 * the remaining memory for other CPU's is allocated by the 177 * linker script 178 */ 179 . = ALIGN(CACHE_WRITEBACK_GRANULE); 180 __PMF_TIMESTAMP_START__ = .; 181 KEEP(*(pmf_timestamp_array)) 182 . = ALIGN(CACHE_WRITEBACK_GRANULE); 183 __PMF_PERCPU_TIMESTAMP_END__ = .; 184 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 185 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 186 __PMF_TIMESTAMP_END__ = .; 187#endif /* ENABLE_PMF */ 188 __BSS_END__ = .; 189 } >RAM 190 191 /* 192 * The xlat_table section is for full, aligned page tables (4K). 193 * Removing them from .bss avoids forcing 4K alignment on 194 * the .bss section and eliminates the unecessary zero init 195 */ 196 xlat_table (NOLOAD) : { 197 *(xlat_table) 198 } >RAM 199 200#if USE_COHERENT_MEM 201 /* 202 * The base address of the coherent memory section must be page-aligned (4K) 203 * to guarantee that the coherent data are stored on their own pages and 204 * are not mixed with normal data. This is required to set up the correct 205 * memory attributes for the coherent data page tables. 206 */ 207 coherent_ram (NOLOAD) : ALIGN(4096) { 208 __COHERENT_RAM_START__ = .; 209 /* 210 * Bakery locks are stored in coherent memory 211 * 212 * Each lock's data is contiguous and fully allocated by the compiler 213 */ 214 *(bakery_lock) 215 *(tzfw_coherent_mem) 216 __COHERENT_RAM_END_UNALIGNED__ = .; 217 /* 218 * Memory page(s) mapped to this section will be marked 219 * as device memory. No other unexpected data must creep in. 220 * Ensure the rest of the current memory page is unused. 221 */ 222 . = NEXT(4096); 223 __COHERENT_RAM_END__ = .; 224 } >RAM 225#endif 226 227 /* 228 * Define a linker symbol to mark end of the RW memory area for this 229 * image. 230 */ 231 __RW_END__ = .; 232 __BL31_END__ = .; 233 234 __BSS_SIZE__ = SIZEOF(.bss); 235#if USE_COHERENT_MEM 236 __COHERENT_RAM_UNALIGNED_SIZE__ = 237 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 238#endif 239 240 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 241} 242