1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <stdbool.h> 8 9 #include <arch.h> 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <drivers/arm/gicv3.h> 13 #include <lib/mmio.h> 14 #include <lib/psci/psci.h> 15 16 #include <plat_imx8.h> 17 #include <sci/sci.h> 18 19 const static int ap_core_index[PLATFORM_CORE_COUNT] = { 20 SC_R_A35_0, SC_R_A35_1, SC_R_A35_2, SC_R_A35_3 21 }; 22 23 int imx_pwr_domain_on(u_register_t mpidr) 24 { 25 int ret = PSCI_E_SUCCESS; 26 unsigned int cpu_id; 27 28 cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 29 30 printf("imx_pwr_domain_on cpu_id %d\n", cpu_id); 31 32 if (sc_pm_set_resource_power_mode(ipc_handle, ap_core_index[cpu_id], 33 SC_PM_PW_MODE_ON) != SC_ERR_NONE) { 34 ERROR("core %d power on failed!\n", cpu_id); 35 ret = PSCI_E_INTERN_FAIL; 36 } 37 38 if (sc_pm_cpu_start(ipc_handle, ap_core_index[cpu_id], 39 true, BL31_BASE) != SC_ERR_NONE) { 40 ERROR("boot core %d failed!\n", cpu_id); 41 ret = PSCI_E_INTERN_FAIL; 42 } 43 44 return ret; 45 } 46 47 void imx_pwr_domain_on_finish(const psci_power_state_t *target_state) 48 { 49 plat_gic_pcpu_init(); 50 plat_gic_cpuif_enable(); 51 } 52 53 int imx_validate_ns_entrypoint(uintptr_t ns_entrypoint) 54 { 55 return PSCI_E_SUCCESS; 56 } 57 58 void imx_pwr_domain_off(const psci_power_state_t *target_state) 59 { 60 u_register_t mpidr = read_mpidr_el1(); 61 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 62 63 plat_gic_cpuif_disable(); 64 sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], 65 SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_NONE); 66 printf("turn off core:%d\n", cpu_id); 67 } 68 69 void imx_domain_suspend(const psci_power_state_t *target_state) 70 { 71 u_register_t mpidr = read_mpidr_el1(); 72 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 73 74 plat_gic_cpuif_disable(); 75 76 sc_pm_set_cpu_resume_addr(ipc_handle, ap_core_index[cpu_id], BL31_BASE); 77 sc_pm_req_cpu_low_power_mode(ipc_handle, ap_core_index[cpu_id], 78 SC_PM_PW_MODE_OFF, SC_PM_WAKE_SRC_GIC); 79 } 80 81 void imx_domain_suspend_finish(const psci_power_state_t *target_state) 82 { 83 u_register_t mpidr = read_mpidr_el1(); 84 unsigned int cpu_id = MPIDR_AFFLVL0_VAL(mpidr); 85 86 sc_pm_req_low_power_mode(ipc_handle, ap_core_index[cpu_id], 87 SC_PM_PW_MODE_ON); 88 89 plat_gic_cpuif_enable(); 90 } 91 92 static const plat_psci_ops_t imx_plat_psci_ops = { 93 .pwr_domain_on = imx_pwr_domain_on, 94 .pwr_domain_on_finish = imx_pwr_domain_on_finish, 95 .validate_ns_entrypoint = imx_validate_ns_entrypoint, 96 .system_off = imx_system_off, 97 .system_reset = imx_system_reset, 98 .pwr_domain_off = imx_pwr_domain_off, 99 .pwr_domain_suspend = imx_domain_suspend, 100 .pwr_domain_suspend_finish = imx_domain_suspend_finish, 101 .get_sys_suspend_power_state = imx_get_sys_suspend_power_state, 102 .validate_power_state = imx_validate_power_state, 103 }; 104 105 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 106 const plat_psci_ops_t **psci_ops) 107 { 108 imx_mailbox_init(sec_entrypoint); 109 *psci_ops = &imx_plat_psci_ops; 110 111 /* Request low power mode for A35 cluster, only need to do once */ 112 sc_pm_req_low_power_mode(ipc_handle, SC_R_A35, SC_PM_PW_MODE_OFF); 113 114 /* Request RUN and LP modes for DDR, system interconnect etc. */ 115 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, 116 SC_PM_SYS_IF_DDR, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 117 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, 118 SC_PM_SYS_IF_MU, SC_PM_PW_MODE_ON, SC_PM_PW_MODE_STBY); 119 sc_pm_req_sys_if_power_mode(ipc_handle, SC_R_A35, 120 SC_PM_SYS_IF_INTERCONNECT, SC_PM_PW_MODE_ON, 121 SC_PM_PW_MODE_STBY); 122 123 return 0; 124 } 125