1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <cassert.h> 12 #include <common_def.h> 13 #include <platform_def.h> 14 #include <sys/types.h> 15 #include <utils.h> 16 #include <xlat_tables_v2.h> 17 #include "../xlat_tables_private.h" 18 19 #if defined(IMAGE_BL1) || defined(IMAGE_BL31) 20 # define IMAGE_EL 3 21 #else 22 # define IMAGE_EL 1 23 #endif 24 25 static unsigned long long tcr_ps_bits; 26 27 static unsigned long long calc_physical_addr_size_bits( 28 unsigned long long max_addr) 29 { 30 /* Physical address can't exceed 48 bits */ 31 assert((max_addr & ADDR_MASK_48_TO_63) == 0); 32 33 /* 48 bits address */ 34 if (max_addr & ADDR_MASK_44_TO_47) 35 return TCR_PS_BITS_256TB; 36 37 /* 44 bits address */ 38 if (max_addr & ADDR_MASK_42_TO_43) 39 return TCR_PS_BITS_16TB; 40 41 /* 42 bits address */ 42 if (max_addr & ADDR_MASK_40_TO_41) 43 return TCR_PS_BITS_4TB; 44 45 /* 40 bits address */ 46 if (max_addr & ADDR_MASK_36_TO_39) 47 return TCR_PS_BITS_1TB; 48 49 /* 36 bits address */ 50 if (max_addr & ADDR_MASK_32_TO_35) 51 return TCR_PS_BITS_64GB; 52 53 return TCR_PS_BITS_4GB; 54 } 55 56 #if ENABLE_ASSERTIONS 57 /* Physical Address ranges supported in the AArch64 Memory Model */ 58 static const unsigned int pa_range_bits_arr[] = { 59 PARANGE_0000, PARANGE_0001, PARANGE_0010, PARANGE_0011, PARANGE_0100, 60 PARANGE_0101 61 }; 62 63 unsigned long long xlat_arch_get_max_supported_pa(void) 64 { 65 u_register_t pa_range = read_id_aa64mmfr0_el1() & 66 ID_AA64MMFR0_EL1_PARANGE_MASK; 67 68 /* All other values are reserved */ 69 assert(pa_range < ARRAY_SIZE(pa_range_bits_arr)); 70 71 return (1ull << pa_range_bits_arr[pa_range]) - 1ull; 72 } 73 #endif /* ENABLE_ASSERTIONS*/ 74 75 int is_mmu_enabled(void) 76 { 77 #if IMAGE_EL == 1 78 assert(IS_IN_EL(1)); 79 return (read_sctlr_el1() & SCTLR_M_BIT) != 0; 80 #elif IMAGE_EL == 3 81 assert(IS_IN_EL(3)); 82 return (read_sctlr_el3() & SCTLR_M_BIT) != 0; 83 #endif 84 } 85 86 #if PLAT_XLAT_TABLES_DYNAMIC 87 88 void xlat_arch_tlbi_va(uintptr_t va) 89 { 90 /* 91 * Ensure the translation table write has drained into memory before 92 * invalidating the TLB entry. 93 */ 94 dsbishst(); 95 96 #if IMAGE_EL == 1 97 assert(IS_IN_EL(1)); 98 tlbivaae1is(TLBI_ADDR(va)); 99 #elif IMAGE_EL == 3 100 assert(IS_IN_EL(3)); 101 tlbivae3is(TLBI_ADDR(va)); 102 #endif 103 } 104 105 void xlat_arch_tlbi_va_sync(void) 106 { 107 /* 108 * A TLB maintenance instruction can complete at any time after 109 * it is issued, but is only guaranteed to be complete after the 110 * execution of DSB by the PE that executed the TLB maintenance 111 * instruction. After the TLB invalidate instruction is 112 * complete, no new memory accesses using the invalidated TLB 113 * entries will be observed by any observer of the system 114 * domain. See section D4.8.2 of the ARMv8 (issue k), paragraph 115 * "Ordering and completion of TLB maintenance instructions". 116 */ 117 dsbish(); 118 119 /* 120 * The effects of a completed TLB maintenance instruction are 121 * only guaranteed to be visible on the PE that executed the 122 * instruction after the execution of an ISB instruction by the 123 * PE that executed the TLB maintenance instruction. 124 */ 125 isb(); 126 } 127 128 #endif /* PLAT_XLAT_TABLES_DYNAMIC */ 129 130 void init_xlat_tables_arch(unsigned long long max_pa) 131 { 132 assert((PLAT_PHY_ADDR_SPACE_SIZE - 1) <= 133 xlat_arch_get_max_supported_pa()); 134 135 /* 136 * If dynamic allocation of new regions is enabled the code can't make 137 * assumptions about the max physical address because it could change 138 * after adding new regions. If this functionality is disabled it is 139 * safer to restrict the max physical address as much as possible. 140 */ 141 #ifdef PLAT_XLAT_TABLES_DYNAMIC 142 tcr_ps_bits = calc_physical_addr_size_bits(PLAT_PHY_ADDR_SPACE_SIZE); 143 #else 144 tcr_ps_bits = calc_physical_addr_size_bits(max_pa); 145 #endif 146 } 147 148 /******************************************************************************* 149 * Macro generating the code for the function enabling the MMU in the given 150 * exception level, assuming that the pagetables have already been created. 151 * 152 * _el: Exception level at which the function will run 153 * _tcr_extra: Extra bits to set in the TCR register. This mask will 154 * be OR'ed with the default TCR value. 155 * _tlbi_fct: Function to invalidate the TLBs at the current 156 * exception level 157 ******************************************************************************/ 158 #define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct) \ 159 void enable_mmu_internal_el##_el(unsigned int flags, \ 160 uint64_t *base_table) \ 161 { \ 162 uint64_t mair, tcr, ttbr; \ 163 uint32_t sctlr; \ 164 \ 165 assert(IS_IN_EL(_el)); \ 166 assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0); \ 167 \ 168 /* Invalidate TLBs at the current exception level */ \ 169 _tlbi_fct(); \ 170 \ 171 /* Set attributes in the right indices of the MAIR */ \ 172 mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX); \ 173 mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, \ 174 ATTR_IWBWA_OWBWA_NTR_INDEX); \ 175 mair |= MAIR_ATTR_SET(ATTR_NON_CACHEABLE, \ 176 ATTR_NON_CACHEABLE_INDEX); \ 177 write_mair_el##_el(mair); \ 178 \ 179 /* Set TCR bits as well. */ \ 180 /* Set T0SZ to (64 - width of virtual address space) */ \ 181 if (flags & XLAT_TABLE_NC) { \ 182 /* Inner & outer non-cacheable non-shareable. */\ 183 tcr = TCR_SH_NON_SHAREABLE | \ 184 TCR_RGN_OUTER_NC | TCR_RGN_INNER_NC | \ 185 (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\ 186 } else { \ 187 /* Inner & outer WBWA & shareable. */ \ 188 tcr = TCR_SH_INNER_SHAREABLE | \ 189 TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | \ 190 (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE));\ 191 } \ 192 tcr |= _tcr_extra; \ 193 write_tcr_el##_el(tcr); \ 194 \ 195 /* Set TTBR bits as well */ \ 196 ttbr = (uint64_t) base_table; \ 197 write_ttbr0_el##_el(ttbr); \ 198 \ 199 /* Ensure all translation table writes have drained */ \ 200 /* into memory, the TLB invalidation is complete, */ \ 201 /* and translation register writes are committed */ \ 202 /* before enabling the MMU */ \ 203 dsbish(); \ 204 isb(); \ 205 \ 206 sctlr = read_sctlr_el##_el(); \ 207 sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \ 208 \ 209 if (flags & DISABLE_DCACHE) \ 210 sctlr &= ~SCTLR_C_BIT; \ 211 else \ 212 sctlr |= SCTLR_C_BIT; \ 213 \ 214 write_sctlr_el##_el(sctlr); \ 215 \ 216 /* Ensure the MMU enable takes effect immediately */ \ 217 isb(); \ 218 } 219 220 /* Define EL1 and EL3 variants of the function enabling the MMU */ 221 #if IMAGE_EL == 1 222 DEFINE_ENABLE_MMU_EL(1, 223 (tcr_ps_bits << TCR_EL1_IPS_SHIFT), 224 tlbivmalle1) 225 #elif IMAGE_EL == 3 226 DEFINE_ENABLE_MMU_EL(3, 227 TCR_EL3_RES1 | (tcr_ps_bits << TCR_EL3_PS_SHIFT), 228 tlbialle3) 229 #endif 230 231 void enable_mmu_arch(unsigned int flags, uint64_t *base_table) 232 { 233 #if IMAGE_EL == 1 234 assert(IS_IN_EL(1)); 235 enable_mmu_internal_el1(flags, base_table); 236 #elif IMAGE_EL == 3 237 assert(IS_IN_EL(3)); 238 enable_mmu_internal_el3(flags, base_table); 239 #endif 240 } 241