1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <common/interrupt_props.h> 16 #include <drivers/arm/cci.h> 17 #include <drivers/arm/gicv2.h> 18 #include <drivers/arm/pl011.h> 19 #include <lib/mmio.h> 20 21 #include <hi6220.h> 22 #include <hikey_def.h> 23 #include <hisi_ipc.h> 24 #include <hisi_pwrc.h> 25 26 #include "hikey_private.h" 27 28 /* 29 * The next 2 constants identify the extents of the code & RO data region. 30 * These addresses are used by the MMU setup code and therefore they must be 31 * page-aligned. It is the responsibility of the linker script to ensure that 32 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 33 */ 34 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 35 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 36 37 /* 38 * The next 2 constants identify the extents of the coherent memory region. 39 * These addresses are used by the MMU setup code and therefore they must be 40 * page-aligned. It is the responsibility of the linker script to ensure that 41 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 42 * page-aligned addresses. 43 */ 44 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 45 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 46 47 static entry_point_info_t bl32_ep_info; 48 static entry_point_info_t bl33_ep_info; 49 static console_pl011_t console; 50 51 /****************************************************************************** 52 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 53 * interrupts. 54 *****************************************************************************/ 55 static const interrupt_prop_t g0_interrupt_props[] = { 56 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 57 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 58 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 59 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 60 }; 61 62 /* 63 * Ideally `arm_gic_data` structure definition should be a `const` but it is 64 * kept as modifiable for overwriting with different GICD and GICC base when 65 * running on FVP with VE memory map. 66 */ 67 gicv2_driver_data_t hikey_gic_data = { 68 .gicd_base = PLAT_ARM_GICD_BASE, 69 .gicc_base = PLAT_ARM_GICC_BASE, 70 .interrupt_props = g0_interrupt_props, 71 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 72 }; 73 74 static const int cci_map[] = { 75 CCI400_SL_IFACE3_CLUSTER_IX, 76 CCI400_SL_IFACE4_CLUSTER_IX 77 }; 78 79 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 80 { 81 entry_point_info_t *next_image_info; 82 83 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 84 85 /* None of the images on this platform can have 0x0 as the entrypoint */ 86 if (next_image_info->pc) 87 return next_image_info; 88 return NULL; 89 } 90 91 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 92 u_register_t arg2, u_register_t arg3) 93 { 94 void *from_bl2; 95 96 from_bl2 = (void *) arg0; 97 98 /* Initialize the console to provide early debug support */ 99 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 100 PL011_BAUDRATE, &console); 101 102 /* Initialize CCI driver */ 103 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 104 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 105 106 /* 107 * Check params passed from BL2 should not be NULL, 108 */ 109 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 110 assert(params_from_bl2 != NULL); 111 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 112 assert(params_from_bl2->h.version >= VERSION_2); 113 114 bl_params_node_t *bl_params = params_from_bl2->head; 115 116 /* 117 * Copy BL33 and BL32 (if present), entry point information. 118 * They are stored in Secure RAM, in BL2's address space. 119 */ 120 while (bl_params) { 121 if (bl_params->image_id == BL32_IMAGE_ID) 122 bl32_ep_info = *bl_params->ep_info; 123 124 if (bl_params->image_id == BL33_IMAGE_ID) 125 bl33_ep_info = *bl_params->ep_info; 126 127 bl_params = bl_params->next_params_info; 128 } 129 130 if (bl33_ep_info.pc == 0) 131 panic(); 132 } 133 134 void bl31_plat_arch_setup(void) 135 { 136 hikey_init_mmu_el3(BL31_BASE, 137 BL31_LIMIT - BL31_BASE, 138 BL31_RO_BASE, 139 BL31_RO_LIMIT, 140 BL31_COHERENT_RAM_BASE, 141 BL31_COHERENT_RAM_LIMIT); 142 } 143 144 /* Initialize EDMAC controller with non-secure mode. */ 145 static void hikey_edma_init(void) 146 { 147 int i; 148 uint32_t non_secure; 149 150 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 151 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 152 153 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) { 154 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 155 } 156 } 157 158 void bl31_platform_setup(void) 159 { 160 /* Initialize the GIC driver, cpu and distributor interfaces */ 161 gicv2_driver_init(&hikey_gic_data); 162 gicv2_distif_init(); 163 gicv2_pcpu_distif_init(); 164 gicv2_cpuif_enable(); 165 166 hikey_edma_init(); 167 168 hisi_ipc_init(); 169 hisi_pwrc_setup(); 170 } 171 172 void bl31_plat_runtime_setup(void) 173 { 174 } 175