1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include <tsp.h> 34#include <xlat_tables.h> 35#include "../tsp_private.h" 36 37 38 .globl tsp_entrypoint 39 .globl tsp_vector_table 40 41 42 43 /* --------------------------------------------- 44 * Populate the params in x0-x7 from the pointer 45 * to the smc args structure in x0. 46 * --------------------------------------------- 47 */ 48 .macro restore_args_call_smc 49 ldp x6, x7, [x0, #TSP_ARG6] 50 ldp x4, x5, [x0, #TSP_ARG4] 51 ldp x2, x3, [x0, #TSP_ARG2] 52 ldp x0, x1, [x0, #TSP_ARG0] 53 smc #0 54 .endm 55 56 .macro save_eret_context reg1 reg2 57 mrs \reg1, elr_el1 58 mrs \reg2, spsr_el1 59 stp \reg1, \reg2, [sp, #-0x10]! 60 stp x30, x18, [sp, #-0x10]! 61 .endm 62 63 .macro restore_eret_context reg1 reg2 64 ldp x30, x18, [sp], #0x10 65 ldp \reg1, \reg2, [sp], #0x10 66 msr elr_el1, \reg1 67 msr spsr_el1, \reg2 68 .endm 69 70 .section .text, "ax" 71 .align 3 72 73func tsp_entrypoint 74 75 /* --------------------------------------------- 76 * Set the exception vector to something sane. 77 * --------------------------------------------- 78 */ 79 adr x0, tsp_exceptions 80 msr vbar_el1, x0 81 82 /* --------------------------------------------- 83 * Enable the instruction cache, stack pointer 84 * and data access alignment checks 85 * --------------------------------------------- 86 */ 87 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 88 mrs x0, sctlr_el1 89 orr x0, x0, x1 90 msr sctlr_el1, x0 91 isb 92 93 /* --------------------------------------------- 94 * Zero out NOBITS sections. There are 2 of them: 95 * - the .bss section; 96 * - the coherent memory section. 97 * --------------------------------------------- 98 */ 99 ldr x0, =__BSS_START__ 100 ldr x1, =__BSS_SIZE__ 101 bl zeromem16 102 103 ldr x0, =__COHERENT_RAM_START__ 104 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ 105 bl zeromem16 106 107 /* -------------------------------------------- 108 * Allocate a stack whose memory will be marked 109 * as Normal-IS-WBWA when the MMU is enabled. 110 * There is no risk of reading stale stack 111 * memory after enabling the MMU as only the 112 * primary cpu is running at the moment. 113 * -------------------------------------------- 114 */ 115 mrs x0, mpidr_el1 116 bl platform_set_stack 117 118 /* --------------------------------------------- 119 * Perform early platform setup & platform 120 * specific early arch. setup e.g. mmu setup 121 * --------------------------------------------- 122 */ 123 bl tsp_early_platform_setup 124 bl tsp_plat_arch_setup 125 126 /* --------------------------------------------- 127 * Jump to main function. 128 * --------------------------------------------- 129 */ 130 bl tsp_main 131 132 /* --------------------------------------------- 133 * Tell TSPD that we are done initialising 134 * --------------------------------------------- 135 */ 136 mov x1, x0 137 mov x0, #TSP_ENTRY_DONE 138 smc #0 139 140tsp_entrypoint_panic: 141 b tsp_entrypoint_panic 142 143 144 /* ------------------------------------------- 145 * Table of entrypoint vectors provided to the 146 * TSPD for the various entrypoints 147 * ------------------------------------------- 148 */ 149func tsp_vector_table 150 b tsp_std_smc_entry 151 b tsp_fast_smc_entry 152 b tsp_cpu_on_entry 153 b tsp_cpu_off_entry 154 b tsp_cpu_resume_entry 155 b tsp_cpu_suspend_entry 156 b tsp_fiq_entry 157 158 /*--------------------------------------------- 159 * This entrypoint is used by the TSPD when this 160 * cpu is to be turned off through a CPU_OFF 161 * psci call to ask the TSP to perform any 162 * bookeeping necessary. In the current 163 * implementation, the TSPD expects the TSP to 164 * re-initialise its state so nothing is done 165 * here except for acknowledging the request. 166 * --------------------------------------------- 167 */ 168func tsp_cpu_off_entry 169 bl tsp_cpu_off_main 170 restore_args_call_smc 171 172 /*--------------------------------------------- 173 * This entrypoint is used by the TSPD when this 174 * cpu is turned on using a CPU_ON psci call to 175 * ask the TSP to initialise itself i.e. setup 176 * the mmu, stacks etc. Minimal architectural 177 * state will be initialised by the TSPD when 178 * this function is entered i.e. Caches and MMU 179 * will be turned off, the execution state 180 * will be aarch64 and exceptions masked. 181 * --------------------------------------------- 182 */ 183func tsp_cpu_on_entry 184 /* --------------------------------------------- 185 * Set the exception vector to something sane. 186 * --------------------------------------------- 187 */ 188 adr x0, tsp_exceptions 189 msr vbar_el1, x0 190 191 /* --------------------------------------------- 192 * Enable the instruction cache, stack pointer 193 * and data access alignment checks 194 * --------------------------------------------- 195 */ 196 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) 197 mrs x0, sctlr_el1 198 orr x0, x0, x1 199 msr sctlr_el1, x0 200 isb 201 202 /* -------------------------------------------- 203 * Give ourselves a stack whose memory will be 204 * marked as Normal-IS-WBWA when the MMU is 205 * enabled. 206 * -------------------------------------------- 207 */ 208 mrs x0, mpidr_el1 209 bl platform_set_stack 210 211 /* -------------------------------------------- 212 * Enable the MMU with the DCache disabled. It 213 * is safe to use stacks allocated in normal 214 * memory as a result. All memory accesses are 215 * marked nGnRnE when the MMU is disabled. So 216 * all the stack writes will make it to memory. 217 * All memory accesses are marked Non-cacheable 218 * when the MMU is enabled but D$ is disabled. 219 * So used stack memory is guaranteed to be 220 * visible immediately after the MMU is enabled 221 * Enabling the DCache at the same time as the 222 * MMU can lead to speculatively fetched and 223 * possibly stale stack memory being read from 224 * other caches. This can lead to coherency 225 * issues. 226 * -------------------------------------------- 227 */ 228 mov x0, #DISABLE_DCACHE 229 bl bl32_plat_enable_mmu 230 231 /* --------------------------------------------- 232 * Enable the Data cache now that the MMU has 233 * been enabled. The stack has been unwound. It 234 * will be written first before being read. This 235 * will invalidate any stale cache lines resi- 236 * -dent in other caches. We assume that 237 * interconnect coherency has been enabled for 238 * this cluster by EL3 firmware. 239 * --------------------------------------------- 240 */ 241 mrs x0, sctlr_el1 242 orr x0, x0, #SCTLR_C_BIT 243 msr sctlr_el1, x0 244 isb 245 246 /* --------------------------------------------- 247 * Enter C runtime to perform any remaining 248 * book keeping 249 * --------------------------------------------- 250 */ 251 bl tsp_cpu_on_main 252 restore_args_call_smc 253 254 /* Should never reach here */ 255tsp_cpu_on_entry_panic: 256 b tsp_cpu_on_entry_panic 257 258 /*--------------------------------------------- 259 * This entrypoint is used by the TSPD when this 260 * cpu is to be suspended through a CPU_SUSPEND 261 * psci call to ask the TSP to perform any 262 * bookeeping necessary. In the current 263 * implementation, the TSPD saves and restores 264 * the EL1 state. 265 * --------------------------------------------- 266 */ 267func tsp_cpu_suspend_entry 268 bl tsp_cpu_suspend_main 269 restore_args_call_smc 270 271 /*--------------------------------------------- 272 * This entrypoint is used by the TSPD to pass 273 * control for handling a pending S-EL1 FIQ. 274 * 'x0' contains a magic number which indicates 275 * this. TSPD expects control to be handed back 276 * at the end of FIQ processing. This is done 277 * through an SMC. The handover agreement is: 278 * 279 * 1. PSTATE.DAIF are set upon entry. 'x1' has 280 * the ELR_EL3 from the non-secure state. 281 * 2. TSP has to preserve the callee saved 282 * general purpose registers, SP_EL1/EL0 and 283 * LR. 284 * 3. TSP has to preserve the system and vfp 285 * registers (if applicable). 286 * 4. TSP can use 'x0-x18' to enable its C 287 * runtime. 288 * 5. TSP returns to TSPD using an SMC with 289 * 'x0' = TSP_HANDLED_S_EL1_FIQ 290 * --------------------------------------------- 291 */ 292func tsp_fiq_entry 293#if DEBUG 294 mov x2, #(TSP_HANDLE_FIQ_AND_RETURN & ~0xffff) 295 movk x2, #(TSP_HANDLE_FIQ_AND_RETURN & 0xffff) 296 cmp x0, x2 297 b.ne tsp_fiq_entry_panic 298#endif 299 /*--------------------------------------------- 300 * Save any previous context needed to perform 301 * an exception return from S-EL1 e.g. context 302 * from a previous IRQ. Update statistics and 303 * handle the FIQ before returning to the TSPD. 304 * IRQ/FIQs are not enabled since that will 305 * complicate the implementation. Execution 306 * will be transferred back to the normal world 307 * in any case. A non-zero return value from the 308 * fiq handler is an error. 309 * --------------------------------------------- 310 */ 311 save_eret_context x2 x3 312 bl tsp_update_sync_fiq_stats 313 bl tsp_fiq_handler 314 cbnz x0, tsp_fiq_entry_panic 315 restore_eret_context x2 x3 316 mov x0, #(TSP_HANDLED_S_EL1_FIQ & ~0xffff) 317 movk x0, #(TSP_HANDLED_S_EL1_FIQ & 0xffff) 318 smc #0 319 320tsp_fiq_entry_panic: 321 b tsp_fiq_entry_panic 322 323 /*--------------------------------------------- 324 * This entrypoint is used by the TSPD when this 325 * cpu resumes execution after an earlier 326 * CPU_SUSPEND psci call to ask the TSP to 327 * restore its saved context. In the current 328 * implementation, the TSPD saves and restores 329 * EL1 state so nothing is done here apart from 330 * acknowledging the request. 331 * --------------------------------------------- 332 */ 333func tsp_cpu_resume_entry 334 bl tsp_cpu_resume_main 335 restore_args_call_smc 336tsp_cpu_resume_panic: 337 b tsp_cpu_resume_panic 338 339 /*--------------------------------------------- 340 * This entrypoint is used by the TSPD to ask 341 * the TSP to service a fast smc request. 342 * --------------------------------------------- 343 */ 344func tsp_fast_smc_entry 345 bl tsp_smc_handler 346 restore_args_call_smc 347tsp_fast_smc_entry_panic: 348 b tsp_fast_smc_entry_panic 349 350 /*--------------------------------------------- 351 * This entrypoint is used by the TSPD to ask 352 * the TSP to service a std smc request. 353 * We will enable preemption during execution 354 * of tsp_smc_handler. 355 * --------------------------------------------- 356 */ 357func tsp_std_smc_entry 358 msr daifclr, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 359 bl tsp_smc_handler 360 msr daifset, #DAIF_FIQ_BIT | DAIF_IRQ_BIT 361 restore_args_call_smc 362tsp_std_smc_entry_panic: 363 b tsp_std_smc_entry_panic 364