1 /* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_config.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <errno.h> 12 #include <mmio.h> 13 #include <platform.h> 14 #include <plat_arm.h> 15 #include <psci.h> 16 #include <v2m_def.h> 17 #include "drivers/pwrc/fvp_pwrc.h" 18 #include "fvp_def.h" 19 #include "fvp_private.h" 20 21 22 #if ARM_RECOM_STATE_ID_ENC 23 /* 24 * The table storing the valid idle power states. Ensure that the 25 * array entries are populated in ascending order of state-id to 26 * enable us to use binary search during power state validation. 27 * The table must be terminated by a NULL entry. 28 */ 29 const unsigned int arm_pm_idle_states[] = { 30 /* State-id - 0x01 */ 31 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RET, 32 ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 33 /* State-id - 0x02 */ 34 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 35 ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 36 /* State-id - 0x22 */ 37 arm_make_pwrstate_lvl1(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 38 ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 39 0, 40 }; 41 #endif 42 43 /******************************************************************************* 44 * Function which implements the common FVP specific operations to power down a 45 * cluster in response to a CPU_OFF or CPU_SUSPEND request. 46 ******************************************************************************/ 47 static void fvp_cluster_pwrdwn_common(void) 48 { 49 uint64_t mpidr = read_mpidr_el1(); 50 51 /* Disable coherency if this cluster is to be turned off */ 52 fvp_interconnect_disable(); 53 54 /* Program the power controller to turn the cluster off */ 55 fvp_pwrc_write_pcoffr(mpidr); 56 } 57 58 static void fvp_power_domain_on_finish_common(const psci_power_state_t *target_state) 59 { 60 unsigned long mpidr; 61 62 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 63 ARM_LOCAL_STATE_OFF); 64 65 /* Get the mpidr for this cpu */ 66 mpidr = read_mpidr_el1(); 67 68 /* Perform the common cluster specific operations */ 69 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 70 ARM_LOCAL_STATE_OFF) { 71 /* 72 * This CPU might have woken up whilst the cluster was 73 * attempting to power down. In this case the FVP power 74 * controller will have a pending cluster power off request 75 * which needs to be cleared by writing to the PPONR register. 76 * This prevents the power controller from interpreting a 77 * subsequent entry of this cpu into a simple wfi as a power 78 * down request. 79 */ 80 fvp_pwrc_write_pponr(mpidr); 81 82 /* Enable coherency if this cluster was off */ 83 fvp_interconnect_enable(); 84 } 85 86 /* 87 * Clear PWKUPR.WEN bit to ensure interrupts do not interfere 88 * with a cpu power down unless the bit is set again 89 */ 90 fvp_pwrc_clr_wen(mpidr); 91 } 92 93 94 /******************************************************************************* 95 * FVP handler called when a CPU is about to enter standby. 96 ******************************************************************************/ 97 void fvp_cpu_standby(plat_local_state_t cpu_state) 98 { 99 100 assert(cpu_state == ARM_LOCAL_STATE_RET); 101 102 /* 103 * Enter standby state 104 * dsb is good practice before using wfi to enter low power states 105 */ 106 dsb(); 107 wfi(); 108 } 109 110 /******************************************************************************* 111 * FVP handler called when a power domain is about to be turned on. The 112 * mpidr determines the CPU to be turned on. 113 ******************************************************************************/ 114 int fvp_pwr_domain_on(u_register_t mpidr) 115 { 116 int rc = PSCI_E_SUCCESS; 117 unsigned int psysr; 118 119 /* 120 * Ensure that we do not cancel an inflight power off request for the 121 * target cpu. That would leave it in a zombie wfi. Wait for it to power 122 * off and then program the power controller to turn that CPU on. 123 */ 124 do { 125 psysr = fvp_pwrc_read_psysr(mpidr); 126 } while (psysr & PSYSR_AFF_L0); 127 128 fvp_pwrc_write_pponr(mpidr); 129 return rc; 130 } 131 132 /******************************************************************************* 133 * FVP handler called when a power domain is about to be turned off. The 134 * target_state encodes the power state that each level should transition to. 135 ******************************************************************************/ 136 void fvp_pwr_domain_off(const psci_power_state_t *target_state) 137 { 138 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 139 ARM_LOCAL_STATE_OFF); 140 141 /* 142 * If execution reaches this stage then this power domain will be 143 * suspended. Perform at least the cpu specific actions followed 144 * by the cluster specific operations if applicable. 145 */ 146 147 /* Prevent interrupts from spuriously waking up this cpu */ 148 plat_arm_gic_cpuif_disable(); 149 150 /* Turn redistributor off */ 151 plat_arm_gic_redistif_off(); 152 153 /* Program the power controller to power off this cpu. */ 154 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 155 156 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 157 ARM_LOCAL_STATE_OFF) 158 fvp_cluster_pwrdwn_common(); 159 160 } 161 162 /******************************************************************************* 163 * FVP handler called when a power domain is about to be suspended. The 164 * target_state encodes the power state that each level should transition to. 165 ******************************************************************************/ 166 void fvp_pwr_domain_suspend(const psci_power_state_t *target_state) 167 { 168 unsigned long mpidr; 169 170 /* 171 * FVP has retention only at cpu level. Just return 172 * as nothing is to be done for retention. 173 */ 174 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 175 ARM_LOCAL_STATE_RET) 176 return; 177 178 assert(target_state->pwr_domain_state[ARM_PWR_LVL0] == 179 ARM_LOCAL_STATE_OFF); 180 181 /* Get the mpidr for this cpu */ 182 mpidr = read_mpidr_el1(); 183 184 /* Program the power controller to enable wakeup interrupts. */ 185 fvp_pwrc_set_wen(mpidr); 186 187 /* Prevent interrupts from spuriously waking up this cpu */ 188 plat_arm_gic_cpuif_disable(); 189 190 /* 191 * The Redistributor is not powered off as it can potentially prevent 192 * wake up events reaching the CPUIF and/or might lead to losing 193 * register context. 194 */ 195 196 /* Program the power controller to power off this cpu. */ 197 fvp_pwrc_write_ppoffr(read_mpidr_el1()); 198 199 /* Perform the common cluster specific operations */ 200 if (target_state->pwr_domain_state[ARM_PWR_LVL1] == 201 ARM_LOCAL_STATE_OFF) 202 fvp_cluster_pwrdwn_common(); 203 } 204 205 /******************************************************************************* 206 * FVP handler called when a power domain has just been powered on after 207 * being turned off earlier. The target_state encodes the low power state that 208 * each level has woken up from. 209 ******************************************************************************/ 210 void fvp_pwr_domain_on_finish(const psci_power_state_t *target_state) 211 { 212 fvp_power_domain_on_finish_common(target_state); 213 214 /* Enable the gic cpu interface */ 215 plat_arm_gic_pcpu_init(); 216 217 /* Program the gic per-cpu distributor or re-distributor interface */ 218 plat_arm_gic_cpuif_enable(); 219 } 220 221 /******************************************************************************* 222 * FVP handler called when a power domain has just been powered on after 223 * having been suspended earlier. The target_state encodes the low power state 224 * that each level has woken up from. 225 * TODO: At the moment we reuse the on finisher and reinitialize the secure 226 * context. Need to implement a separate suspend finisher. 227 ******************************************************************************/ 228 void fvp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) 229 { 230 /* 231 * Nothing to be done on waking up from retention from CPU level. 232 */ 233 if (target_state->pwr_domain_state[ARM_PWR_LVL0] == 234 ARM_LOCAL_STATE_RET) 235 return; 236 237 fvp_power_domain_on_finish_common(target_state); 238 239 /* Enable the gic cpu interface */ 240 plat_arm_gic_cpuif_enable(); 241 } 242 243 /******************************************************************************* 244 * FVP handlers to shutdown/reboot the system 245 ******************************************************************************/ 246 static void __dead2 fvp_system_off(void) 247 { 248 /* Write the System Configuration Control Register */ 249 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 250 V2M_CFGCTRL_START | 251 V2M_CFGCTRL_RW | 252 V2M_CFGCTRL_FUNC(V2M_FUNC_SHUTDOWN)); 253 wfi(); 254 ERROR("FVP System Off: operation not handled.\n"); 255 panic(); 256 } 257 258 static void __dead2 fvp_system_reset(void) 259 { 260 /* Write the System Configuration Control Register */ 261 mmio_write_32(V2M_SYSREGS_BASE + V2M_SYS_CFGCTRL, 262 V2M_CFGCTRL_START | 263 V2M_CFGCTRL_RW | 264 V2M_CFGCTRL_FUNC(V2M_FUNC_REBOOT)); 265 wfi(); 266 ERROR("FVP System Reset: operation not handled.\n"); 267 panic(); 268 } 269 270 static int fvp_node_hw_state(u_register_t target_cpu, 271 unsigned int power_level) 272 { 273 unsigned int psysr; 274 int ret; 275 276 /* 277 * The format of 'power_level' is implementation-defined, but 0 must 278 * mean a CPU. We also allow 1 to denote the cluster 279 */ 280 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) 281 return PSCI_E_INVALID_PARAMS; 282 283 /* 284 * Read the status of the given MPDIR from FVP power controller. The 285 * power controller only gives us on/off status, so map that to expected 286 * return values of the PSCI call 287 */ 288 psysr = fvp_pwrc_read_psysr(target_cpu); 289 if (psysr == PSYSR_INVALID) 290 return PSCI_E_INVALID_PARAMS; 291 292 switch (power_level) { 293 case ARM_PWR_LVL0: 294 ret = (psysr & PSYSR_AFF_L0) ? HW_ON : HW_OFF; 295 break; 296 case ARM_PWR_LVL1: 297 ret = (psysr & PSYSR_AFF_L1) ? HW_ON : HW_OFF; 298 break; 299 default: 300 assert(0); 301 } 302 303 return ret; 304 } 305 306 /******************************************************************************* 307 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 308 * platform layer will take care of registering the handlers with PSCI. 309 ******************************************************************************/ 310 plat_psci_ops_t plat_arm_psci_pm_ops = { 311 .cpu_standby = fvp_cpu_standby, 312 .pwr_domain_on = fvp_pwr_domain_on, 313 .pwr_domain_off = fvp_pwr_domain_off, 314 .pwr_domain_suspend = fvp_pwr_domain_suspend, 315 .pwr_domain_on_finish = fvp_pwr_domain_on_finish, 316 .pwr_domain_suspend_finish = fvp_pwr_domain_suspend_finish, 317 .system_off = fvp_system_off, 318 .system_reset = fvp_system_reset, 319 .validate_power_state = arm_validate_power_state, 320 .validate_ns_entrypoint = arm_validate_ns_entrypoint, 321 .get_node_hw_state = fvp_node_hw_state 322 }; 323