1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <cci.h> 11 #include <console.h> 12 #include <debug.h> 13 #include <errno.h> 14 #include <gicv2.h> 15 #include <hi6220.h> 16 #include <hikey_def.h> 17 #include <hisi_ipc.h> 18 #include <hisi_pwrc.h> 19 #include <interrupt_props.h> 20 #include <mmio.h> 21 #include <platform_def.h> 22 23 #include "hikey_private.h" 24 25 /* 26 * The next 2 constants identify the extents of the code & RO data region. 27 * These addresses are used by the MMU setup code and therefore they must be 28 * page-aligned. It is the responsibility of the linker script to ensure that 29 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 30 */ 31 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 32 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 33 34 /* 35 * The next 2 constants identify the extents of the coherent memory region. 36 * These addresses are used by the MMU setup code and therefore they must be 37 * page-aligned. It is the responsibility of the linker script to ensure that 38 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 39 * page-aligned addresses. 40 */ 41 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 42 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 43 44 static entry_point_info_t bl32_ep_info; 45 static entry_point_info_t bl33_ep_info; 46 47 /****************************************************************************** 48 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 49 * interrupts. 50 *****************************************************************************/ 51 static const interrupt_prop_t g0_interrupt_props[] = { 52 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 53 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 54 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 55 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 56 }; 57 58 /* 59 * Ideally `arm_gic_data` structure definition should be a `const` but it is 60 * kept as modifiable for overwriting with different GICD and GICC base when 61 * running on FVP with VE memory map. 62 */ 63 gicv2_driver_data_t hikey_gic_data = { 64 .gicd_base = PLAT_ARM_GICD_BASE, 65 .gicc_base = PLAT_ARM_GICC_BASE, 66 .interrupt_props = g0_interrupt_props, 67 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 68 }; 69 70 static const int cci_map[] = { 71 CCI400_SL_IFACE3_CLUSTER_IX, 72 CCI400_SL_IFACE4_CLUSTER_IX 73 }; 74 75 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 76 { 77 entry_point_info_t *next_image_info; 78 79 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info; 80 81 /* None of the images on this platform can have 0x0 as the entrypoint */ 82 if (next_image_info->pc) 83 return next_image_info; 84 return NULL; 85 } 86 87 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 88 u_register_t arg2, u_register_t arg3) 89 { 90 void *from_bl2; 91 92 from_bl2 = (void *) arg0; 93 94 /* Initialize the console to provide early debug support */ 95 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 96 97 /* Initialize CCI driver */ 98 cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map)); 99 cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); 100 101 /* 102 * Check params passed from BL2 should not be NULL, 103 */ 104 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 105 assert(params_from_bl2 != NULL); 106 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 107 assert(params_from_bl2->h.version >= VERSION_2); 108 109 bl_params_node_t *bl_params = params_from_bl2->head; 110 111 /* 112 * Copy BL33 and BL32 (if present), entry point information. 113 * They are stored in Secure RAM, in BL2's address space. 114 */ 115 while (bl_params) { 116 if (bl_params->image_id == BL32_IMAGE_ID) 117 bl32_ep_info = *bl_params->ep_info; 118 119 if (bl_params->image_id == BL33_IMAGE_ID) 120 bl33_ep_info = *bl_params->ep_info; 121 122 bl_params = bl_params->next_params_info; 123 } 124 125 if (bl33_ep_info.pc == 0) 126 panic(); 127 } 128 129 void bl31_plat_arch_setup(void) 130 { 131 hikey_init_mmu_el3(BL31_BASE, 132 BL31_LIMIT - BL31_BASE, 133 BL31_RO_BASE, 134 BL31_RO_LIMIT, 135 BL31_COHERENT_RAM_BASE, 136 BL31_COHERENT_RAM_LIMIT); 137 } 138 139 /* Initialize EDMAC controller with non-secure mode. */ 140 static void hikey_edma_init(void) 141 { 142 int i; 143 uint32_t non_secure; 144 145 non_secure = EDMAC_SEC_CTRL_INTR_SEC | EDMAC_SEC_CTRL_GLOBAL_SEC; 146 mmio_write_32(EDMAC_SEC_CTRL, non_secure); 147 148 for (i = 0; i < EDMAC_CHANNEL_NUMS; i++) { 149 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18)); 150 } 151 } 152 153 void bl31_platform_setup(void) 154 { 155 /* Initialize the GIC driver, cpu and distributor interfaces */ 156 gicv2_driver_init(&hikey_gic_data); 157 gicv2_distif_init(); 158 gicv2_pcpu_distif_init(); 159 gicv2_cpuif_enable(); 160 161 hikey_edma_init(); 162 163 hisi_ipc_init(); 164 hisi_pwrc_setup(); 165 } 166 167 void bl31_plat_runtime_setup(void) 168 { 169 } 170