1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLATFORM_DEF_H__ 8 #define __PLATFORM_DEF_H__ 9 10 #include "mt8173_def.h" 11 12 13 /******************************************************************************* 14 * Platform binary types for linking 15 ******************************************************************************/ 16 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 17 #define PLATFORM_LINKER_ARCH aarch64 18 19 /******************************************************************************* 20 * Generic platform constants 21 ******************************************************************************/ 22 23 /* Size of cacheable stacks */ 24 #if defined(IMAGE_BL1) 25 #define PLATFORM_STACK_SIZE 0x440 26 #elif defined(IMAGE_BL2) 27 #define PLATFORM_STACK_SIZE 0x400 28 #elif defined(IMAGE_BL31) 29 #define PLATFORM_STACK_SIZE 0x800 30 #elif defined(IMAGE_BL32) 31 #define PLATFORM_STACK_SIZE 0x440 32 #endif 33 34 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 35 36 #define PLATFORM_MAX_AFFLVL MPIDR_AFFLVL2 37 #if !ENABLE_PLAT_COMPAT 38 #define PLAT_MAX_PWR_LVL 2 39 #define PLAT_MAX_RET_STATE 1 40 #define PLAT_MAX_OFF_STATE 2 41 #endif 42 #define PLATFORM_SYSTEM_COUNT 1 43 #define PLATFORM_CLUSTER_COUNT 2 44 #define PLATFORM_CLUSTER0_CORE_COUNT 4 45 #define PLATFORM_CLUSTER1_CORE_COUNT 2 46 #define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \ 47 PLATFORM_CLUSTER0_CORE_COUNT) 48 #define PLATFORM_MAX_CPUS_PER_CLUSTER 4 49 #define PLATFORM_NUM_AFFS (PLATFORM_SYSTEM_COUNT + \ 50 PLATFORM_CLUSTER_COUNT + \ 51 PLATFORM_CORE_COUNT) 52 53 /******************************************************************************* 54 * Platform memory map related constants 55 ******************************************************************************/ 56 /* 57 * MT8173 SRAM memory layout 58 * 0x100000 +-------------------+ 59 * | shared mem (4KB) | 60 * 0x101000 +-------------------+ 61 * | | 62 * | BL3-1 (124KB) | 63 * | | 64 * 0x120000 +-------------------+ 65 * | reserved (64KB) | 66 * 0x130000 +-------------------+ 67 */ 68 /* TF txet, ro, rw, xlat table, coherent memory ... etc. 69 * Size: release: 128KB, debug: 128KB 70 */ 71 #define TZRAM_BASE (0x100000) 72 #if DEBUG 73 #define TZRAM_SIZE (0x20000) 74 #else 75 #define TZRAM_SIZE (0x20000) 76 #endif 77 78 /* Reserved: 64KB */ 79 #define TZRAM2_BASE (TZRAM_BASE + TZRAM_SIZE) 80 #define TZRAM2_SIZE (0x10000) 81 82 /******************************************************************************* 83 * BL31 specific defines. 84 ******************************************************************************/ 85 /* 86 * Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if 87 * present). BL31_BASE is calculated using the current BL3-1 debug size plus a 88 * little space for growth. 89 */ 90 #define BL31_BASE (TZRAM_BASE + 0x1000) 91 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 92 #define TZRAM2_LIMIT (TZRAM2_BASE + TZRAM2_SIZE) 93 94 /******************************************************************************* 95 * Platform specific page table and MMU setup constants 96 ******************************************************************************/ 97 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 98 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 99 #define MAX_XLAT_TABLES 4 100 #define MAX_MMAP_REGIONS 16 101 102 /******************************************************************************* 103 * Declarations and constants to access the mailboxes safely. Each mailbox is 104 * aligned on the biggest cache line size in the platform. This is known only 105 * to the platform as it might have a combination of integrated and external 106 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 107 * line at any cache level. They could belong to different cpus/clusters & 108 * get written while being protected by different locks causing corruption of 109 * a valid mailbox address. 110 ******************************************************************************/ 111 #define CACHE_WRITEBACK_SHIFT 6 112 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 113 114 115 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 116 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 117 118 #define PLAT_ARM_G1S_IRQS MT_IRQ_SEC_SGI_0, \ 119 MT_IRQ_SEC_SGI_1, \ 120 MT_IRQ_SEC_SGI_2, \ 121 MT_IRQ_SEC_SGI_3, \ 122 MT_IRQ_SEC_SGI_4, \ 123 MT_IRQ_SEC_SGI_5, \ 124 MT_IRQ_SEC_SGI_6, \ 125 MT_IRQ_SEC_SGI_7 126 127 #define PLAT_ARM_G0_IRQS 128 129 #endif /* __PLATFORM_DEF_H__ */ 130