1 /* 2 * Copyright (c) 2018, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <debug.h> 11 #include <delay_timer.h> 12 #include <dt-bindings/clock/stm32mp1-clks.h> 13 #include <dt-bindings/reset/stm32mp1-resets.h> 14 #include <errno.h> 15 #include <libfdt.h> 16 #include <mmc.h> 17 #include <mmio.h> 18 #include <platform.h> 19 #include <stm32_sdmmc2.h> 20 #include <stm32mp1_clk.h> 21 #include <stm32mp1_dt.h> 22 #include <stm32mp1_rcc.h> 23 #include <stm32mp1_reset.h> 24 #include <string.h> 25 #include <utils.h> 26 27 /* Registers offsets */ 28 #define SDMMC_POWER 0x00U 29 #define SDMMC_CLKCR 0x04U 30 #define SDMMC_ARGR 0x08U 31 #define SDMMC_CMDR 0x0CU 32 #define SDMMC_RESPCMDR 0x10U 33 #define SDMMC_RESP1R 0x14U 34 #define SDMMC_RESP2R 0x18U 35 #define SDMMC_RESP3R 0x1CU 36 #define SDMMC_RESP4R 0x20U 37 #define SDMMC_DTIMER 0x24U 38 #define SDMMC_DLENR 0x28U 39 #define SDMMC_DCTRLR 0x2CU 40 #define SDMMC_DCNTR 0x30U 41 #define SDMMC_STAR 0x34U 42 #define SDMMC_ICR 0x38U 43 #define SDMMC_MASKR 0x3CU 44 #define SDMMC_ACKTIMER 0x40U 45 #define SDMMC_IDMACTRLR 0x50U 46 #define SDMMC_IDMABSIZER 0x54U 47 #define SDMMC_IDMABASE0R 0x58U 48 #define SDMMC_IDMABASE1R 0x5CU 49 #define SDMMC_FIFOR 0x80U 50 51 /* SDMMC power control register */ 52 #define SDMMC_POWER_PWRCTRL GENMASK(1, 0) 53 #define SDMMC_POWER_DIRPOL BIT(4) 54 55 /* SDMMC clock control register */ 56 #define SDMMC_CLKCR_WIDBUS_4 BIT(14) 57 #define SDMMC_CLKCR_WIDBUS_8 BIT(15) 58 #define SDMMC_CLKCR_NEGEDGE BIT(16) 59 #define SDMMC_CLKCR_HWFC_EN BIT(17) 60 #define SDMMC_CLKCR_SELCLKRX_0 BIT(20) 61 62 /* SDMMC command register */ 63 #define SDMMC_CMDR_CMDTRANS BIT(6) 64 #define SDMMC_CMDR_CMDSTOP BIT(7) 65 #define SDMMC_CMDR_WAITRESP GENMASK(9, 8) 66 #define SDMMC_CMDR_WAITRESP_SHORT BIT(8) 67 #define SDMMC_CMDR_WAITRESP_SHORT_NOCRC BIT(9) 68 #define SDMMC_CMDR_CPSMEN BIT(12) 69 70 /* SDMMC data control register */ 71 #define SDMMC_DCTRLR_DTEN BIT(0) 72 #define SDMMC_DCTRLR_DTDIR BIT(1) 73 #define SDMMC_DCTRLR_DTMODE GENMASK(3, 2) 74 #define SDMMC_DCTRLR_DBLOCKSIZE_0 BIT(4) 75 #define SDMMC_DCTRLR_DBLOCKSIZE_1 BIT(5) 76 #define SDMMC_DCTRLR_DBLOCKSIZE_3 BIT(7) 77 #define SDMMC_DCTRLR_DBLOCKSIZE GENMASK(7, 4) 78 #define SDMMC_DCTRLR_FIFORST BIT(13) 79 80 #define SDMMC_DCTRLR_CLEAR_MASK (SDMMC_DCTRLR_DTEN | \ 81 SDMMC_DCTRLR_DTDIR | \ 82 SDMMC_DCTRLR_DTMODE | \ 83 SDMMC_DCTRLR_DBLOCKSIZE) 84 #define SDMMC_DBLOCKSIZE_8 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 85 SDMMC_DCTRLR_DBLOCKSIZE_1) 86 #define SDMMC_DBLOCKSIZE_512 (SDMMC_DCTRLR_DBLOCKSIZE_0 | \ 87 SDMMC_DCTRLR_DBLOCKSIZE_3) 88 89 /* SDMMC status register */ 90 #define SDMMC_STAR_CCRCFAIL BIT(0) 91 #define SDMMC_STAR_DCRCFAIL BIT(1) 92 #define SDMMC_STAR_CTIMEOUT BIT(2) 93 #define SDMMC_STAR_DTIMEOUT BIT(3) 94 #define SDMMC_STAR_TXUNDERR BIT(4) 95 #define SDMMC_STAR_RXOVERR BIT(5) 96 #define SDMMC_STAR_CMDREND BIT(6) 97 #define SDMMC_STAR_CMDSENT BIT(7) 98 #define SDMMC_STAR_DATAEND BIT(8) 99 #define SDMMC_STAR_DBCKEND BIT(10) 100 #define SDMMC_STAR_DPSMACT BIT(11) 101 #define SDMMC_STAR_RXFIFOHF BIT(15) 102 #define SDMMC_STAR_RXFIFOE BIT(19) 103 #define SDMMC_STAR_IDMATE BIT(27) 104 #define SDMMC_STAR_IDMABTC BIT(28) 105 106 /* SDMMC DMA control register */ 107 #define SDMMC_IDMACTRLR_IDMAEN BIT(0) 108 109 #define SDMMC_STATIC_FLAGS (SDMMC_STAR_CCRCFAIL | \ 110 SDMMC_STAR_DCRCFAIL | \ 111 SDMMC_STAR_CTIMEOUT | \ 112 SDMMC_STAR_DTIMEOUT | \ 113 SDMMC_STAR_TXUNDERR | \ 114 SDMMC_STAR_RXOVERR | \ 115 SDMMC_STAR_CMDREND | \ 116 SDMMC_STAR_CMDSENT | \ 117 SDMMC_STAR_DATAEND | \ 118 SDMMC_STAR_DBCKEND | \ 119 SDMMC_STAR_IDMATE | \ 120 SDMMC_STAR_IDMABTC) 121 122 #define TIMEOUT_10_MS (plat_get_syscnt_freq2() / 100U) 123 #define TIMEOUT_1_S plat_get_syscnt_freq2() 124 125 #define DT_SDMMC2_COMPAT "st,stm32-sdmmc2" 126 127 static void stm32_sdmmc2_init(void); 128 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd); 129 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd); 130 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width); 131 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size); 132 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size); 133 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size); 134 135 static const struct mmc_ops stm32_sdmmc2_ops = { 136 .init = stm32_sdmmc2_init, 137 .send_cmd = stm32_sdmmc2_send_cmd, 138 .set_ios = stm32_sdmmc2_set_ios, 139 .prepare = stm32_sdmmc2_prepare, 140 .read = stm32_sdmmc2_read, 141 .write = stm32_sdmmc2_write, 142 }; 143 144 static struct stm32_sdmmc2_params sdmmc2_params; 145 146 #pragma weak plat_sdmmc2_use_dma 147 bool plat_sdmmc2_use_dma(unsigned int instance, unsigned int memory) 148 { 149 return false; 150 } 151 152 static void stm32_sdmmc2_init(void) 153 { 154 uint32_t clock_div; 155 uintptr_t base = sdmmc2_params.reg_base; 156 157 clock_div = div_round_up(sdmmc2_params.clk_rate, 158 STM32MP1_MMC_INIT_FREQ * 2); 159 160 mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div | 161 sdmmc2_params.negedge | 162 sdmmc2_params.pin_ckin); 163 164 mmio_write_32(base + SDMMC_POWER, 165 SDMMC_POWER_PWRCTRL | sdmmc2_params.dirpol); 166 167 mdelay(1); 168 } 169 170 static int stm32_sdmmc2_stop_transfer(void) 171 { 172 struct mmc_cmd cmd_stop; 173 174 zeromem(&cmd_stop, sizeof(struct mmc_cmd)); 175 176 cmd_stop.cmd_idx = MMC_CMD(12); 177 cmd_stop.resp_type = MMC_RESPONSE_R1B; 178 179 return stm32_sdmmc2_send_cmd(&cmd_stop); 180 } 181 182 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd) 183 { 184 uint32_t flags_cmd, status; 185 uint32_t flags_data = 0; 186 int err = 0; 187 uintptr_t base = sdmmc2_params.reg_base; 188 unsigned int cmd_reg, arg_reg, start; 189 190 if (cmd == NULL) { 191 return -EINVAL; 192 } 193 194 flags_cmd = SDMMC_STAR_CTIMEOUT; 195 arg_reg = cmd->cmd_arg; 196 197 if ((mmio_read_32(base + SDMMC_CMDR) & SDMMC_CMDR_CPSMEN) != 0U) { 198 mmio_write_32(base + SDMMC_CMDR, 0); 199 } 200 201 cmd_reg = cmd->cmd_idx | SDMMC_CMDR_CPSMEN; 202 203 if (cmd->resp_type == 0U) { 204 flags_cmd |= SDMMC_STAR_CMDSENT; 205 } 206 207 if ((cmd->resp_type & MMC_RSP_48) != 0U) { 208 if ((cmd->resp_type & MMC_RSP_136) != 0U) { 209 flags_cmd |= SDMMC_STAR_CMDREND; 210 cmd_reg |= SDMMC_CMDR_WAITRESP; 211 } else if ((cmd->resp_type & MMC_RSP_CRC) != 0U) { 212 flags_cmd |= SDMMC_STAR_CMDREND | SDMMC_STAR_CCRCFAIL; 213 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT; 214 } else { 215 flags_cmd |= SDMMC_STAR_CMDREND; 216 cmd_reg |= SDMMC_CMDR_WAITRESP_SHORT_NOCRC; 217 } 218 } 219 220 switch (cmd->cmd_idx) { 221 case MMC_CMD(1): 222 arg_reg |= OCR_POWERUP; 223 break; 224 case MMC_CMD(8): 225 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 226 cmd_reg |= SDMMC_CMDR_CMDTRANS; 227 } 228 break; 229 case MMC_CMD(12): 230 cmd_reg |= SDMMC_CMDR_CMDSTOP; 231 break; 232 case MMC_CMD(17): 233 case MMC_CMD(18): 234 cmd_reg |= SDMMC_CMDR_CMDTRANS; 235 if (sdmmc2_params.use_dma) { 236 flags_data |= SDMMC_STAR_DCRCFAIL | 237 SDMMC_STAR_DTIMEOUT | 238 SDMMC_STAR_DATAEND | 239 SDMMC_STAR_RXOVERR | 240 SDMMC_STAR_IDMATE; 241 } 242 break; 243 case MMC_ACMD(41): 244 arg_reg |= OCR_3_2_3_3 | OCR_3_3_3_4; 245 break; 246 case MMC_ACMD(51): 247 cmd_reg |= SDMMC_CMDR_CMDTRANS; 248 if (sdmmc2_params.use_dma) { 249 flags_data |= SDMMC_STAR_DCRCFAIL | 250 SDMMC_STAR_DTIMEOUT | 251 SDMMC_STAR_DATAEND | 252 SDMMC_STAR_RXOVERR | 253 SDMMC_STAR_IDMATE | 254 SDMMC_STAR_DBCKEND; 255 } 256 break; 257 default: 258 break; 259 } 260 261 if ((cmd->resp_type & MMC_RSP_BUSY) != 0U) { 262 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 263 } 264 265 mmio_write_32(base + SDMMC_ARGR, arg_reg); 266 267 mmio_write_32(base + SDMMC_CMDR, cmd_reg); 268 269 start = get_timer(0); 270 271 do { 272 status = mmio_read_32(base + SDMMC_STAR); 273 274 if (get_timer(start) > TIMEOUT_10_MS) { 275 err = -ETIMEDOUT; 276 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 277 __func__, cmd->cmd_idx, status); 278 break; 279 } 280 } while ((status & flags_cmd) == 0U); 281 282 if (((status & (SDMMC_STAR_CTIMEOUT | SDMMC_STAR_CCRCFAIL)) != 0U) && 283 (err == 0)) { 284 if ((status & SDMMC_STAR_CTIMEOUT) != 0U) { 285 err = -ETIMEDOUT; 286 /* 287 * Those timeouts can occur, and framework will handle 288 * the retries. CMD8 is expected to return this timeout 289 * for eMMC 290 */ 291 if (!((cmd->cmd_idx == MMC_CMD(1)) || 292 (cmd->cmd_idx == MMC_CMD(13)) || 293 ((cmd->cmd_idx == MMC_CMD(8)) && 294 (cmd->resp_type == MMC_RESPONSE_R7)))) { 295 ERROR("%s: CTIMEOUT (cmd = %d,status = %x)\n", 296 __func__, cmd->cmd_idx, status); 297 } 298 } else { 299 err = -EIO; 300 ERROR("%s: CRCFAIL (cmd = %d,status = %x)\n", 301 __func__, cmd->cmd_idx, status); 302 } 303 } 304 305 if (((cmd_reg & SDMMC_CMDR_WAITRESP) != 0U) && (err == 0)) { 306 if ((cmd->cmd_idx == MMC_CMD(9)) && 307 ((cmd_reg & SDMMC_CMDR_WAITRESP) == SDMMC_CMDR_WAITRESP)) { 308 /* Need to invert response to match CSD structure */ 309 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP4R); 310 cmd->resp_data[1] = mmio_read_32(base + SDMMC_RESP3R); 311 cmd->resp_data[2] = mmio_read_32(base + SDMMC_RESP2R); 312 cmd->resp_data[3] = mmio_read_32(base + SDMMC_RESP1R); 313 } else { 314 cmd->resp_data[0] = mmio_read_32(base + SDMMC_RESP1R); 315 if ((cmd_reg & SDMMC_CMDR_WAITRESP) == 316 SDMMC_CMDR_WAITRESP) { 317 cmd->resp_data[1] = mmio_read_32(base + 318 SDMMC_RESP2R); 319 cmd->resp_data[2] = mmio_read_32(base + 320 SDMMC_RESP3R); 321 cmd->resp_data[3] = mmio_read_32(base + 322 SDMMC_RESP4R); 323 } 324 } 325 } 326 327 if ((flags_data == 0U) || (err != 0)) { 328 if (flags_data != 0U) { 329 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 330 } 331 332 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 333 334 if ((err != 0) && (flags_data != 0U)) { 335 return stm32_sdmmc2_stop_transfer(); 336 } 337 338 return err; 339 } 340 341 start = get_timer(0); 342 343 do { 344 status = mmio_read_32(base + SDMMC_STAR); 345 346 if (get_timer(start) > TIMEOUT_10_MS) { 347 ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n", 348 __func__, cmd->cmd_idx, status); 349 err = -ETIMEDOUT; 350 break; 351 } 352 } while ((status & flags_data) == 0U); 353 354 if ((status & (SDMMC_STAR_DTIMEOUT | SDMMC_STAR_DCRCFAIL | 355 SDMMC_STAR_TXUNDERR | SDMMC_STAR_RXOVERR | 356 SDMMC_STAR_IDMATE)) != 0U) { 357 ERROR("%s: Error flag (cmd = %d,status = %x)\n", __func__, 358 cmd->cmd_idx, status); 359 err = -EIO; 360 } 361 362 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 363 mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS); 364 365 if (err != 0) { 366 return stm32_sdmmc2_stop_transfer(); 367 } 368 369 return err; 370 } 371 372 static int stm32_sdmmc2_send_cmd(struct mmc_cmd *cmd) 373 { 374 int8_t retry; 375 int err = 0; 376 377 assert(cmd != NULL); 378 379 for (retry = 0; retry <= 3; retry++) { 380 err = stm32_sdmmc2_send_cmd_req(cmd); 381 if (err == 0) { 382 return err; 383 } 384 385 if ((cmd->cmd_idx == MMC_CMD(1)) || 386 (cmd->cmd_idx == MMC_CMD(13))) { 387 return 0; /* Retry managed by framework */ 388 } 389 390 /* Command 8 is expected to fail for eMMC */ 391 if (!(cmd->cmd_idx == MMC_CMD(8))) { 392 WARN(" CMD%d, Retry: %d, Error: %d\n", 393 cmd->cmd_idx, retry, err); 394 } 395 396 udelay(10); 397 } 398 399 return err; 400 } 401 402 static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width) 403 { 404 uintptr_t base = sdmmc2_params.reg_base; 405 uint32_t bus_cfg = 0; 406 uint32_t clock_div, max_freq; 407 uint32_t clk_rate = sdmmc2_params.clk_rate; 408 uint32_t max_bus_freq = sdmmc2_params.device_info->max_bus_freq; 409 410 switch (width) { 411 case MMC_BUS_WIDTH_1: 412 break; 413 case MMC_BUS_WIDTH_4: 414 bus_cfg |= SDMMC_CLKCR_WIDBUS_4; 415 break; 416 case MMC_BUS_WIDTH_8: 417 bus_cfg |= SDMMC_CLKCR_WIDBUS_8; 418 break; 419 default: 420 panic(); 421 break; 422 } 423 424 if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) { 425 if (max_bus_freq >= 52000000U) { 426 max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ; 427 } else { 428 max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ; 429 } 430 } else { 431 if (max_bus_freq >= 50000000U) { 432 max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ; 433 } else { 434 max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ; 435 } 436 } 437 438 clock_div = div_round_up(clk_rate, max_freq * 2); 439 440 mmio_write_32(base + SDMMC_CLKCR, 441 SDMMC_CLKCR_HWFC_EN | clock_div | bus_cfg | 442 sdmmc2_params.negedge | 443 sdmmc2_params.pin_ckin); 444 445 return 0; 446 } 447 448 static int stm32_sdmmc2_prepare(int lba, uintptr_t buf, size_t size) 449 { 450 struct mmc_cmd cmd; 451 int ret; 452 uintptr_t base = sdmmc2_params.reg_base; 453 uint32_t data_ctrl = SDMMC_DCTRLR_DTDIR; 454 455 if (size == 8U) { 456 data_ctrl |= SDMMC_DBLOCKSIZE_8; 457 } else { 458 data_ctrl |= SDMMC_DBLOCKSIZE_512; 459 } 460 461 sdmmc2_params.use_dma = plat_sdmmc2_use_dma(base, buf); 462 463 if (sdmmc2_params.use_dma) { 464 inv_dcache_range(buf, size); 465 } 466 467 /* Prepare CMD 16*/ 468 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 469 470 mmio_write_32(base + SDMMC_DLENR, 0); 471 472 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 473 SDMMC_DCTRLR_CLEAR_MASK, SDMMC_DCTRLR_DTDIR); 474 475 zeromem(&cmd, sizeof(struct mmc_cmd)); 476 477 cmd.cmd_idx = MMC_CMD(16); 478 if (size > MMC_BLOCK_SIZE) { 479 cmd.cmd_arg = MMC_BLOCK_SIZE; 480 } else { 481 cmd.cmd_arg = size; 482 } 483 484 cmd.resp_type = MMC_RESPONSE_R1; 485 486 ret = stm32_sdmmc2_send_cmd(&cmd); 487 if (ret != 0) { 488 ERROR("CMD16 failed\n"); 489 return ret; 490 } 491 492 /* Prepare data command */ 493 mmio_write_32(base + SDMMC_DTIMER, UINT32_MAX); 494 495 mmio_write_32(base + SDMMC_DLENR, size); 496 497 if (sdmmc2_params.use_dma) { 498 mmio_write_32(base + SDMMC_IDMACTRLR, 499 SDMMC_IDMACTRLR_IDMAEN); 500 mmio_write_32(base + SDMMC_IDMABASE0R, buf); 501 502 flush_dcache_range(buf, size); 503 } 504 505 mmio_clrsetbits_32(base + SDMMC_DCTRLR, 506 SDMMC_DCTRLR_CLEAR_MASK, 507 data_ctrl); 508 509 return 0; 510 } 511 512 static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size) 513 { 514 uint32_t error_flags = SDMMC_STAR_RXOVERR | SDMMC_STAR_DCRCFAIL | 515 SDMMC_STAR_DTIMEOUT; 516 uint32_t flags = error_flags | SDMMC_STAR_DATAEND; 517 uint32_t status; 518 uint32_t *buffer; 519 uintptr_t base = sdmmc2_params.reg_base; 520 uintptr_t fifo_reg = base + SDMMC_FIFOR; 521 unsigned int start; 522 int ret; 523 524 /* Assert buf is 4 bytes aligned */ 525 assert((buf & GENMASK(1, 0)) == 0U); 526 527 buffer = (uint32_t *)buf; 528 529 if (sdmmc2_params.use_dma) { 530 inv_dcache_range(buf, size); 531 532 return 0; 533 } 534 535 if (size <= MMC_BLOCK_SIZE) { 536 flags |= SDMMC_STAR_DBCKEND; 537 } 538 539 start = get_timer(0); 540 541 do { 542 status = mmio_read_32(base + SDMMC_STAR); 543 544 if ((status & error_flags) != 0U) { 545 ERROR("%s: Read error (status = %x)\n", __func__, 546 status); 547 mmio_write_32(base + SDMMC_DCTRLR, 548 SDMMC_DCTRLR_FIFORST); 549 550 mmio_write_32(base + SDMMC_ICR, 551 SDMMC_STATIC_FLAGS); 552 553 ret = stm32_sdmmc2_stop_transfer(); 554 if (ret != 0) { 555 return ret; 556 } 557 558 return -EIO; 559 } 560 561 if (get_timer(start) > TIMEOUT_1_S) { 562 ERROR("%s: timeout 1s (status = %x)\n", 563 __func__, status); 564 mmio_write_32(base + SDMMC_ICR, 565 SDMMC_STATIC_FLAGS); 566 567 ret = stm32_sdmmc2_stop_transfer(); 568 if (ret != 0) { 569 return ret; 570 } 571 572 return -ETIMEDOUT; 573 } 574 575 if (size < (8U * sizeof(uint32_t))) { 576 if ((mmio_read_32(base + SDMMC_DCNTR) > 0U) && 577 ((status & SDMMC_STAR_RXFIFOE) == 0U)) { 578 *buffer = mmio_read_32(fifo_reg); 579 buffer++; 580 } 581 } else if ((status & SDMMC_STAR_RXFIFOHF) != 0U) { 582 uint32_t count; 583 584 /* Read data from SDMMC Rx FIFO */ 585 for (count = 0; count < 8U; count++) { 586 *buffer = mmio_read_32(fifo_reg); 587 buffer++; 588 } 589 } 590 } while ((status & flags) == 0U); 591 592 mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS); 593 594 if ((status & SDMMC_STAR_DPSMACT) != 0U) { 595 WARN("%s: DPSMACT=1, send stop\n", __func__); 596 return stm32_sdmmc2_stop_transfer(); 597 } 598 599 return 0; 600 } 601 602 static int stm32_sdmmc2_write(int lba, uintptr_t buf, size_t size) 603 { 604 return 0; 605 } 606 607 static int stm32_sdmmc2_dt_get_config(void) 608 { 609 int sdmmc_node; 610 void *fdt = NULL; 611 const fdt32_t *cuint; 612 613 if (fdt_get_address(&fdt) == 0) { 614 return -FDT_ERR_NOTFOUND; 615 } 616 617 if (fdt == NULL) { 618 return -FDT_ERR_NOTFOUND; 619 } 620 621 sdmmc_node = fdt_node_offset_by_compatible(fdt, -1, DT_SDMMC2_COMPAT); 622 623 while (sdmmc_node != -FDT_ERR_NOTFOUND) { 624 cuint = fdt_getprop(fdt, sdmmc_node, "reg", NULL); 625 if (cuint == NULL) { 626 continue; 627 } 628 629 if (fdt32_to_cpu(*cuint) == sdmmc2_params.reg_base) { 630 break; 631 } 632 633 sdmmc_node = fdt_node_offset_by_compatible(fdt, sdmmc_node, 634 DT_SDMMC2_COMPAT); 635 } 636 637 if (sdmmc_node == -FDT_ERR_NOTFOUND) { 638 return -FDT_ERR_NOTFOUND; 639 } 640 641 if (fdt_check_status(sdmmc_node) == 0) { 642 return -FDT_ERR_NOTFOUND; 643 } 644 645 if (dt_set_pinctrl_config(sdmmc_node) != 0) { 646 return -FDT_ERR_BADVALUE; 647 } 648 649 cuint = fdt_getprop(fdt, sdmmc_node, "clocks", NULL); 650 if (cuint == NULL) { 651 return -FDT_ERR_NOTFOUND; 652 } 653 654 cuint++; 655 sdmmc2_params.clock_id = fdt32_to_cpu(*cuint); 656 657 cuint = fdt_getprop(fdt, sdmmc_node, "resets", NULL); 658 if (cuint == NULL) { 659 return -FDT_ERR_NOTFOUND; 660 } 661 662 cuint++; 663 sdmmc2_params.reset_id = fdt32_to_cpu(*cuint); 664 665 if ((fdt_getprop(fdt, sdmmc_node, "st,pin-ckin", NULL)) != NULL) { 666 sdmmc2_params.pin_ckin = SDMMC_CLKCR_SELCLKRX_0; 667 } 668 669 if ((fdt_getprop(fdt, sdmmc_node, "st,dirpol", NULL)) != NULL) { 670 sdmmc2_params.dirpol = SDMMC_POWER_DIRPOL; 671 } 672 673 if ((fdt_getprop(fdt, sdmmc_node, "st,negedge", NULL)) != NULL) { 674 sdmmc2_params.negedge = SDMMC_CLKCR_NEGEDGE; 675 } 676 677 cuint = fdt_getprop(fdt, sdmmc_node, "bus-width", NULL); 678 if (cuint != NULL) { 679 switch (fdt32_to_cpu(*cuint)) { 680 case 4: 681 sdmmc2_params.bus_width = MMC_BUS_WIDTH_4; 682 break; 683 684 case 8: 685 sdmmc2_params.bus_width = MMC_BUS_WIDTH_8; 686 break; 687 688 default: 689 break; 690 } 691 } 692 693 return 0; 694 } 695 696 unsigned long long stm32_sdmmc2_mmc_get_device_size(void) 697 { 698 return sdmmc2_params.device_info->device_size; 699 } 700 701 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params) 702 { 703 int ret; 704 705 assert((params != NULL) && 706 ((params->reg_base & MMC_BLOCK_MASK) == 0U) && 707 ((params->bus_width == MMC_BUS_WIDTH_1) || 708 (params->bus_width == MMC_BUS_WIDTH_4) || 709 (params->bus_width == MMC_BUS_WIDTH_8))); 710 711 memcpy(&sdmmc2_params, params, sizeof(struct stm32_sdmmc2_params)); 712 713 if (stm32_sdmmc2_dt_get_config() != 0) { 714 ERROR("%s: DT error\n", __func__); 715 return -ENOMEM; 716 } 717 718 ret = stm32mp1_clk_enable(sdmmc2_params.clock_id); 719 if (ret != 0) { 720 ERROR("%s: clock %d failed\n", __func__, 721 sdmmc2_params.clock_id); 722 return ret; 723 } 724 725 stm32mp1_reset_assert(sdmmc2_params.reset_id); 726 udelay(2); 727 stm32mp1_reset_deassert(sdmmc2_params.reset_id); 728 mdelay(1); 729 730 sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id); 731 732 return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate, 733 sdmmc2_params.bus_width, sdmmc2_params.flags, 734 sdmmc2_params.device_info); 735 } 736