1 /* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef ARCH_HELPERS_H 8 #define ARCH_HELPERS_H 9 10 #include <cdefs.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <string.h> 14 15 #include <arch.h> 16 17 /********************************************************************** 18 * Macros which create inline functions to read or write CPU system 19 * registers 20 *********************************************************************/ 21 22 #define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 23 static inline u_register_t read_ ## _name(void) \ 24 { \ 25 u_register_t v; \ 26 __asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \ 27 return v; \ 28 } 29 30 #define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \ 31 static inline void write_ ## _name(u_register_t v) \ 32 { \ 33 __asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \ 34 } 35 36 #define SYSREG_WRITE_CONST(reg_name, v) \ 37 __asm__ volatile ("msr " #reg_name ", %0" : : "i" (v)) 38 39 /* Define read function for system register */ 40 #define DEFINE_SYSREG_READ_FUNC(_name) \ 41 _DEFINE_SYSREG_READ_FUNC(_name, _name) 42 43 /* Define read & write function for system register */ 44 #define DEFINE_SYSREG_RW_FUNCS(_name) \ 45 _DEFINE_SYSREG_READ_FUNC(_name, _name) \ 46 _DEFINE_SYSREG_WRITE_FUNC(_name, _name) 47 48 /* Define read & write function for renamed system register */ 49 #define DEFINE_RENAME_SYSREG_RW_FUNCS(_name, _reg_name) \ 50 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \ 51 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 52 53 /* Define read function for renamed system register */ 54 #define DEFINE_RENAME_SYSREG_READ_FUNC(_name, _reg_name) \ 55 _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) 56 57 /* Define write function for renamed system register */ 58 #define DEFINE_RENAME_SYSREG_WRITE_FUNC(_name, _reg_name) \ 59 _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) 60 61 /********************************************************************** 62 * Macros to create inline functions for system instructions 63 *********************************************************************/ 64 65 /* Define function for simple system instruction */ 66 #define DEFINE_SYSOP_FUNC(_op) \ 67 static inline void _op(void) \ 68 { \ 69 __asm__ (#_op); \ 70 } 71 72 /* Define function for system instruction with type specifier */ 73 #define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \ 74 static inline void _op ## _type(void) \ 75 { \ 76 __asm__ (#_op " " #_type); \ 77 } 78 79 /* Define function for system instruction with register parameter */ 80 #define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \ 81 static inline void _op ## _type(uint64_t v) \ 82 { \ 83 __asm__ (#_op " " #_type ", %0" : : "r" (v)); \ 84 } 85 86 /******************************************************************************* 87 * TLB maintenance accessor prototypes 88 ******************************************************************************/ 89 90 #if ERRATA_A57_813419 91 /* 92 * Define function for TLBI instruction with type specifier that implements 93 * the workaround for errata 813419 of Cortex-A57. 94 */ 95 #define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(_type)\ 96 static inline void tlbi ## _type(void) \ 97 { \ 98 __asm__("tlbi " #_type "\n" \ 99 "dsb ish\n" \ 100 "tlbi " #_type); \ 101 } 102 103 /* 104 * Define function for TLBI instruction with register parameter that implements 105 * the workaround for errata 813419 of Cortex-A57. 106 */ 107 #define DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(_type) \ 108 static inline void tlbi ## _type(uint64_t v) \ 109 { \ 110 __asm__("tlbi " #_type ", %0\n" \ 111 "dsb ish\n" \ 112 "tlbi " #_type ", %0" : : "r" (v)); \ 113 } 114 #endif /* ERRATA_A57_813419 */ 115 116 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1) 117 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle1is) 118 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2) 119 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle2is) 120 #if ERRATA_A57_813419 121 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3) 122 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_FUNC(alle3is) 123 #else 124 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3) 125 DEFINE_SYSOP_TYPE_FUNC(tlbi, alle3is) 126 #endif 127 DEFINE_SYSOP_TYPE_FUNC(tlbi, vmalle1) 128 129 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaae1is) 130 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vaale1is) 131 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae2is) 132 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale2is) 133 #if ERRATA_A57_813419 134 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vae3is) 135 DEFINE_TLBIOP_ERRATA_A57_813419_TYPE_PARAM_FUNC(vale3is) 136 #else 137 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vae3is) 138 DEFINE_SYSOP_TYPE_PARAM_FUNC(tlbi, vale3is) 139 #endif 140 141 /******************************************************************************* 142 * Cache maintenance accessor prototypes 143 ******************************************************************************/ 144 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, isw) 145 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cisw) 146 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, csw) 147 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvac) 148 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, ivac) 149 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, civac) 150 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, cvau) 151 DEFINE_SYSOP_TYPE_PARAM_FUNC(dc, zva) 152 153 /******************************************************************************* 154 * Address translation accessor prototypes 155 ******************************************************************************/ 156 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1r) 157 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e1w) 158 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0r) 159 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s12e0w) 160 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e1r) 161 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e2r) 162 DEFINE_SYSOP_TYPE_PARAM_FUNC(at, s1e3r) 163 164 void flush_dcache_range(uintptr_t addr, size_t size); 165 void clean_dcache_range(uintptr_t addr, size_t size); 166 void inv_dcache_range(uintptr_t addr, size_t size); 167 168 void dcsw_op_louis(u_register_t op_type); 169 void dcsw_op_all(u_register_t op_type); 170 171 void disable_mmu_el1(void); 172 void disable_mmu_el3(void); 173 void disable_mmu_icache_el1(void); 174 void disable_mmu_icache_el3(void); 175 176 /******************************************************************************* 177 * Misc. accessor prototypes 178 ******************************************************************************/ 179 180 #define write_daifclr(val) SYSREG_WRITE_CONST(daifclr, val) 181 #define write_daifset(val) SYSREG_WRITE_CONST(daifset, val) 182 183 DEFINE_SYSREG_RW_FUNCS(par_el1) 184 DEFINE_SYSREG_READ_FUNC(id_pfr1_el1) 185 DEFINE_SYSREG_READ_FUNC(id_aa64isar1_el1) 186 DEFINE_SYSREG_READ_FUNC(id_aa64pfr0_el1) 187 DEFINE_SYSREG_READ_FUNC(id_aa64dfr0_el1) 188 DEFINE_SYSREG_READ_FUNC(CurrentEl) 189 DEFINE_SYSREG_READ_FUNC(ctr_el0) 190 DEFINE_SYSREG_RW_FUNCS(daif) 191 DEFINE_SYSREG_RW_FUNCS(spsr_el1) 192 DEFINE_SYSREG_RW_FUNCS(spsr_el2) 193 DEFINE_SYSREG_RW_FUNCS(spsr_el3) 194 DEFINE_SYSREG_RW_FUNCS(elr_el1) 195 DEFINE_SYSREG_RW_FUNCS(elr_el2) 196 DEFINE_SYSREG_RW_FUNCS(elr_el3) 197 198 DEFINE_SYSOP_FUNC(wfi) 199 DEFINE_SYSOP_FUNC(wfe) 200 DEFINE_SYSOP_FUNC(sev) 201 DEFINE_SYSOP_TYPE_FUNC(dsb, sy) 202 DEFINE_SYSOP_TYPE_FUNC(dmb, sy) 203 DEFINE_SYSOP_TYPE_FUNC(dmb, st) 204 DEFINE_SYSOP_TYPE_FUNC(dmb, ld) 205 DEFINE_SYSOP_TYPE_FUNC(dsb, ish) 206 DEFINE_SYSOP_TYPE_FUNC(dsb, nsh) 207 DEFINE_SYSOP_TYPE_FUNC(dsb, ishst) 208 DEFINE_SYSOP_TYPE_FUNC(dmb, oshld) 209 DEFINE_SYSOP_TYPE_FUNC(dmb, oshst) 210 DEFINE_SYSOP_TYPE_FUNC(dmb, osh) 211 DEFINE_SYSOP_TYPE_FUNC(dmb, nshld) 212 DEFINE_SYSOP_TYPE_FUNC(dmb, nshst) 213 DEFINE_SYSOP_TYPE_FUNC(dmb, nsh) 214 DEFINE_SYSOP_TYPE_FUNC(dmb, ishld) 215 DEFINE_SYSOP_TYPE_FUNC(dmb, ishst) 216 DEFINE_SYSOP_TYPE_FUNC(dmb, ish) 217 DEFINE_SYSOP_FUNC(isb) 218 219 static inline void enable_irq(void) 220 { 221 /* 222 * The compiler memory barrier will prevent the compiler from 223 * scheduling non-volatile memory access after the write to the 224 * register. 225 * 226 * This could happen if some initialization code issues non-volatile 227 * accesses to an area used by an interrupt handler, in the assumption 228 * that it is safe as the interrupts are disabled at the time it does 229 * that (according to program order). However, non-volatile accesses 230 * are not necessarily in program order relatively with volatile inline 231 * assembly statements (and volatile accesses). 232 */ 233 COMPILER_BARRIER(); 234 write_daifclr(DAIF_IRQ_BIT); 235 isb(); 236 } 237 238 static inline void enable_fiq(void) 239 { 240 COMPILER_BARRIER(); 241 write_daifclr(DAIF_FIQ_BIT); 242 isb(); 243 } 244 245 static inline void enable_serror(void) 246 { 247 COMPILER_BARRIER(); 248 write_daifclr(DAIF_ABT_BIT); 249 isb(); 250 } 251 252 static inline void enable_debug_exceptions(void) 253 { 254 COMPILER_BARRIER(); 255 write_daifclr(DAIF_DBG_BIT); 256 isb(); 257 } 258 259 static inline void disable_irq(void) 260 { 261 COMPILER_BARRIER(); 262 write_daifset(DAIF_IRQ_BIT); 263 isb(); 264 } 265 266 static inline void disable_fiq(void) 267 { 268 COMPILER_BARRIER(); 269 write_daifset(DAIF_FIQ_BIT); 270 isb(); 271 } 272 273 static inline void disable_serror(void) 274 { 275 COMPILER_BARRIER(); 276 write_daifset(DAIF_ABT_BIT); 277 isb(); 278 } 279 280 static inline void disable_debug_exceptions(void) 281 { 282 COMPILER_BARRIER(); 283 write_daifset(DAIF_DBG_BIT); 284 isb(); 285 } 286 287 #if !ERROR_DEPRECATED 288 uint32_t get_afflvl_shift(uint32_t); 289 uint32_t mpidr_mask_lower_afflvls(uint64_t, uint32_t); 290 291 void __dead2 eret(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 292 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 293 #endif 294 void __dead2 smc(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, 295 uint64_t x4, uint64_t x5, uint64_t x6, uint64_t x7); 296 297 /******************************************************************************* 298 * System register accessor prototypes 299 ******************************************************************************/ 300 DEFINE_SYSREG_READ_FUNC(midr_el1) 301 DEFINE_SYSREG_READ_FUNC(mpidr_el1) 302 DEFINE_SYSREG_READ_FUNC(id_aa64mmfr0_el1) 303 304 DEFINE_SYSREG_RW_FUNCS(scr_el3) 305 DEFINE_SYSREG_RW_FUNCS(hcr_el2) 306 307 DEFINE_SYSREG_RW_FUNCS(vbar_el1) 308 DEFINE_SYSREG_RW_FUNCS(vbar_el2) 309 DEFINE_SYSREG_RW_FUNCS(vbar_el3) 310 311 DEFINE_SYSREG_RW_FUNCS(sctlr_el1) 312 DEFINE_SYSREG_RW_FUNCS(sctlr_el2) 313 DEFINE_SYSREG_RW_FUNCS(sctlr_el3) 314 315 DEFINE_SYSREG_RW_FUNCS(actlr_el1) 316 DEFINE_SYSREG_RW_FUNCS(actlr_el2) 317 DEFINE_SYSREG_RW_FUNCS(actlr_el3) 318 319 DEFINE_SYSREG_RW_FUNCS(esr_el1) 320 DEFINE_SYSREG_RW_FUNCS(esr_el2) 321 DEFINE_SYSREG_RW_FUNCS(esr_el3) 322 323 DEFINE_SYSREG_RW_FUNCS(afsr0_el1) 324 DEFINE_SYSREG_RW_FUNCS(afsr0_el2) 325 DEFINE_SYSREG_RW_FUNCS(afsr0_el3) 326 327 DEFINE_SYSREG_RW_FUNCS(afsr1_el1) 328 DEFINE_SYSREG_RW_FUNCS(afsr1_el2) 329 DEFINE_SYSREG_RW_FUNCS(afsr1_el3) 330 331 DEFINE_SYSREG_RW_FUNCS(far_el1) 332 DEFINE_SYSREG_RW_FUNCS(far_el2) 333 DEFINE_SYSREG_RW_FUNCS(far_el3) 334 335 DEFINE_SYSREG_RW_FUNCS(mair_el1) 336 DEFINE_SYSREG_RW_FUNCS(mair_el2) 337 DEFINE_SYSREG_RW_FUNCS(mair_el3) 338 339 DEFINE_SYSREG_RW_FUNCS(amair_el1) 340 DEFINE_SYSREG_RW_FUNCS(amair_el2) 341 DEFINE_SYSREG_RW_FUNCS(amair_el3) 342 343 DEFINE_SYSREG_READ_FUNC(rvbar_el1) 344 DEFINE_SYSREG_READ_FUNC(rvbar_el2) 345 DEFINE_SYSREG_READ_FUNC(rvbar_el3) 346 347 DEFINE_SYSREG_RW_FUNCS(rmr_el1) 348 DEFINE_SYSREG_RW_FUNCS(rmr_el2) 349 DEFINE_SYSREG_RW_FUNCS(rmr_el3) 350 351 DEFINE_SYSREG_RW_FUNCS(tcr_el1) 352 DEFINE_SYSREG_RW_FUNCS(tcr_el2) 353 DEFINE_SYSREG_RW_FUNCS(tcr_el3) 354 355 DEFINE_SYSREG_RW_FUNCS(ttbr0_el1) 356 DEFINE_SYSREG_RW_FUNCS(ttbr0_el2) 357 DEFINE_SYSREG_RW_FUNCS(ttbr0_el3) 358 359 DEFINE_SYSREG_RW_FUNCS(ttbr1_el1) 360 361 DEFINE_SYSREG_RW_FUNCS(vttbr_el2) 362 363 DEFINE_SYSREG_RW_FUNCS(cptr_el2) 364 DEFINE_SYSREG_RW_FUNCS(cptr_el3) 365 366 DEFINE_SYSREG_RW_FUNCS(cpacr_el1) 367 DEFINE_SYSREG_RW_FUNCS(cntfrq_el0) 368 DEFINE_SYSREG_RW_FUNCS(cnthp_ctl_el2) 369 DEFINE_SYSREG_RW_FUNCS(cnthp_tval_el2) 370 DEFINE_SYSREG_RW_FUNCS(cnthp_cval_el2) 371 DEFINE_SYSREG_RW_FUNCS(cntps_ctl_el1) 372 DEFINE_SYSREG_RW_FUNCS(cntps_tval_el1) 373 DEFINE_SYSREG_RW_FUNCS(cntps_cval_el1) 374 DEFINE_SYSREG_RW_FUNCS(cntp_ctl_el0) 375 DEFINE_SYSREG_RW_FUNCS(cntp_tval_el0) 376 DEFINE_SYSREG_RW_FUNCS(cntp_cval_el0) 377 DEFINE_SYSREG_READ_FUNC(cntpct_el0) 378 DEFINE_SYSREG_RW_FUNCS(cnthctl_el2) 379 380 #define get_cntp_ctl_enable(x) (((x) >> CNTP_CTL_ENABLE_SHIFT) & \ 381 CNTP_CTL_ENABLE_MASK) 382 #define get_cntp_ctl_imask(x) (((x) >> CNTP_CTL_IMASK_SHIFT) & \ 383 CNTP_CTL_IMASK_MASK) 384 #define get_cntp_ctl_istatus(x) (((x) >> CNTP_CTL_ISTATUS_SHIFT) & \ 385 CNTP_CTL_ISTATUS_MASK) 386 387 #define set_cntp_ctl_enable(x) ((x) |= (U(1) << CNTP_CTL_ENABLE_SHIFT)) 388 #define set_cntp_ctl_imask(x) ((x) |= (U(1) << CNTP_CTL_IMASK_SHIFT)) 389 390 #define clr_cntp_ctl_enable(x) ((x) &= ~(U(1) << CNTP_CTL_ENABLE_SHIFT)) 391 #define clr_cntp_ctl_imask(x) ((x) &= ~(U(1) << CNTP_CTL_IMASK_SHIFT)) 392 393 DEFINE_SYSREG_RW_FUNCS(tpidr_el3) 394 395 DEFINE_SYSREG_RW_FUNCS(cntvoff_el2) 396 397 DEFINE_SYSREG_RW_FUNCS(vpidr_el2) 398 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2) 399 400 DEFINE_SYSREG_READ_FUNC(isr_el1) 401 402 DEFINE_SYSREG_RW_FUNCS(mdcr_el2) 403 DEFINE_SYSREG_RW_FUNCS(mdcr_el3) 404 DEFINE_SYSREG_RW_FUNCS(hstr_el2) 405 DEFINE_SYSREG_RW_FUNCS(pmcr_el0) 406 407 /* GICv3 System Registers */ 408 409 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1) 410 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el2, ICC_SRE_EL2) 411 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el3, ICC_SRE_EL3) 412 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_pmr_el1, ICC_PMR_EL1) 413 DEFINE_RENAME_SYSREG_READ_FUNC(icc_rpr_el1, ICC_RPR_EL1) 414 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el3, ICC_IGRPEN1_EL3) 415 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen1_el1, ICC_IGRPEN1_EL1) 416 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0_EL1) 417 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir0_el1, ICC_HPPIR0_EL1) 418 DEFINE_RENAME_SYSREG_READ_FUNC(icc_hppir1_el1, ICC_HPPIR1_EL1) 419 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar0_el1, ICC_IAR0_EL1) 420 DEFINE_RENAME_SYSREG_READ_FUNC(icc_iar1_el1, ICC_IAR1_EL1) 421 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir0_el1, ICC_EOIR0_EL1) 422 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_eoir1_el1, ICC_EOIR1_EL1) 423 DEFINE_RENAME_SYSREG_WRITE_FUNC(icc_sgi0r_el1, ICC_SGI0R_EL1) 424 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sgi1r, ICC_SGI1R) 425 426 DEFINE_RENAME_SYSREG_RW_FUNCS(amcgcr_el0, AMCGCR_EL0) 427 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr0_el0, AMCNTENCLR0_EL0) 428 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset0_el0, AMCNTENSET0_EL0) 429 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenclr1_el0, AMCNTENCLR1_EL0) 430 DEFINE_RENAME_SYSREG_RW_FUNCS(amcntenset1_el0, AMCNTENSET1_EL0) 431 432 DEFINE_RENAME_SYSREG_READ_FUNC(mpamidr_el1, MPAMIDR_EL1) 433 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam3_el3, MPAM3_EL3) 434 DEFINE_RENAME_SYSREG_RW_FUNCS(mpam2_el2, MPAM2_EL2) 435 DEFINE_RENAME_SYSREG_RW_FUNCS(mpamhcr_el2, MPAMHCR_EL2) 436 437 DEFINE_RENAME_SYSREG_RW_FUNCS(pmblimitr_el1, PMBLIMITR_EL1) 438 439 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el3, ZCR_EL3) 440 DEFINE_RENAME_SYSREG_WRITE_FUNC(zcr_el2, ZCR_EL2) 441 442 DEFINE_RENAME_SYSREG_READ_FUNC(erridr_el1, ERRIDR_EL1) 443 DEFINE_RENAME_SYSREG_WRITE_FUNC(errselr_el1, ERRSELR_EL1) 444 445 DEFINE_RENAME_SYSREG_READ_FUNC(erxfr_el1, ERXFR_EL1) 446 DEFINE_RENAME_SYSREG_RW_FUNCS(erxctlr_el1, ERXCTLR_EL1) 447 DEFINE_RENAME_SYSREG_RW_FUNCS(erxstatus_el1, ERXSTATUS_EL1) 448 DEFINE_RENAME_SYSREG_READ_FUNC(erxaddr_el1, ERXADDR_EL1) 449 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc0_el1, ERXMISC0_EL1) 450 DEFINE_RENAME_SYSREG_READ_FUNC(erxmisc1_el1, ERXMISC1_EL1) 451 452 /* Armv8.3 Pointer Authentication Registers */ 453 DEFINE_RENAME_SYSREG_RW_FUNCS(apgakeylo_el1, APGAKeyLo_EL1) 454 455 #define IS_IN_EL(x) \ 456 (GET_EL(read_CurrentEl()) == MODE_EL##x) 457 458 #define IS_IN_EL1() IS_IN_EL(1) 459 #define IS_IN_EL2() IS_IN_EL(2) 460 #define IS_IN_EL3() IS_IN_EL(3) 461 462 static inline unsigned int get_current_el(void) 463 { 464 return GET_EL(read_CurrentEl()); 465 } 466 467 /* 468 * Check if an EL is implemented from AA64PFR0 register fields. 469 */ 470 static inline uint64_t el_implemented(unsigned int el) 471 { 472 if (el > 3U) { 473 return EL_IMPL_NONE; 474 } else { 475 unsigned int shift = ID_AA64PFR0_EL1_SHIFT * el; 476 477 return (read_id_aa64pfr0_el1() >> shift) & ID_AA64PFR0_ELX_MASK; 478 } 479 } 480 481 #if !ERROR_DEPRECATED 482 #define EL_IMPLEMENTED(_el) el_implemented(_el) 483 #endif 484 485 /* Previously defined accesor functions with incomplete register names */ 486 487 #define read_current_el() read_CurrentEl() 488 489 #define dsb() dsbsy() 490 491 #define read_midr() read_midr_el1() 492 493 #define read_mpidr() read_mpidr_el1() 494 495 #define read_scr() read_scr_el3() 496 #define write_scr(_v) write_scr_el3(_v) 497 498 #define read_hcr() read_hcr_el2() 499 #define write_hcr(_v) write_hcr_el2(_v) 500 501 #define read_cpacr() read_cpacr_el1() 502 #define write_cpacr(_v) write_cpacr_el1(_v) 503 504 #endif /* ARCH_HELPERS_H */ 505