1 /* 2 * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef DSU_DEF_H 8 #define DSU_DEF_H 9 10 #include <lib/utils_def.h> 11 12 /******************************************************************** 13 * DSU control registers definitions * 14 ********************************************************************/ 15 #define CLUSTERCFR_EL1 S3_0_C15_C3_0 16 #define CLUSTERIDR_EL1 S3_0_C15_C3_1 17 #define CLUSTERACTLR_EL1 S3_0_C15_C3_3 18 19 /******************************************************************** 20 * DSU control registers bit fields * 21 ********************************************************************/ 22 #define CLUSTERIDR_REV_SHIFT U(0) 23 #define CLUSTERIDR_REV_BITS U(4) 24 #define CLUSTERIDR_VAR_SHIFT U(4) 25 #define CLUSTERIDR_VAR_BITS U(4) 26 #define CLUSTERCFR_ACP_SHIFT U(11) 27 28 /******************************************************************** 29 * Masks applied for DSU errata workarounds * 30 ********************************************************************/ 31 #define DSU_ERRATA_936184_MASK (ULL(0x3) << 15) 32 33 #endif /* DSU_DEF_H */ 34