1/* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6#include <arch.h> 7#include <asm_macros.S> 8#include <common/bl_common.h> 9#include <cortex_a73.h> 10#include <cpu_macros.S> 11#include <plat_macros.S> 12 13 /* --------------------------------------------- 14 * Disable L1 data cache 15 * --------------------------------------------- 16 */ 17func cortex_a73_disable_dcache 18 mrs x1, sctlr_el3 19 bic x1, x1, #SCTLR_C_BIT 20 msr sctlr_el3, x1 21 isb 22 ret 23endfunc cortex_a73_disable_dcache 24 25 /* --------------------------------------------- 26 * Disable intra-cluster coherency 27 * --------------------------------------------- 28 */ 29func cortex_a73_disable_smp 30 mrs x0, CORTEX_A73_CPUECTLR_EL1 31 bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 32 msr CORTEX_A73_CPUECTLR_EL1, x0 33 isb 34 dsb sy 35 ret 36endfunc cortex_a73_disable_smp 37 38func cortex_a73_reset_func 39#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 40 cpu_check_csv2 x0, 1f 41 adr x0, wa_cve_2017_5715_bpiall_vbar 42 msr vbar_el3, x0 43 /* isb will be performed before returning from this function */ 441: 45#endif 46 47#if WORKAROUND_CVE_2018_3639 48 mrs x0, CORTEX_A73_IMP_DEF_REG1 49 orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE 50 msr CORTEX_A73_IMP_DEF_REG1, x0 51 isb 52#endif 53 54 /* --------------------------------------------- 55 * Enable the SMP bit. 56 * Clobbers : x0 57 * --------------------------------------------- 58 */ 59 mrs x0, CORTEX_A73_CPUECTLR_EL1 60 orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT 61 msr CORTEX_A73_CPUECTLR_EL1, x0 62 isb 63 ret 64endfunc cortex_a73_reset_func 65 66func cortex_a73_core_pwr_dwn 67 mov x18, x30 68 69 /* --------------------------------------------- 70 * Turn off caches. 71 * --------------------------------------------- 72 */ 73 bl cortex_a73_disable_dcache 74 75 /* --------------------------------------------- 76 * Flush L1 caches. 77 * --------------------------------------------- 78 */ 79 mov x0, #DCCISW 80 bl dcsw_op_level1 81 82 /* --------------------------------------------- 83 * Come out of intra cluster coherency 84 * --------------------------------------------- 85 */ 86 mov x30, x18 87 b cortex_a73_disable_smp 88endfunc cortex_a73_core_pwr_dwn 89 90func cortex_a73_cluster_pwr_dwn 91 mov x18, x30 92 93 /* --------------------------------------------- 94 * Turn off caches. 95 * --------------------------------------------- 96 */ 97 bl cortex_a73_disable_dcache 98 99 /* --------------------------------------------- 100 * Flush L1 caches. 101 * --------------------------------------------- 102 */ 103 mov x0, #DCCISW 104 bl dcsw_op_level1 105 106 /* --------------------------------------------- 107 * Disable the optional ACP. 108 * --------------------------------------------- 109 */ 110 bl plat_disable_acp 111 112 /* --------------------------------------------- 113 * Flush L2 caches. 114 * --------------------------------------------- 115 */ 116 mov x0, #DCCISW 117 bl dcsw_op_level2 118 119 /* --------------------------------------------- 120 * Come out of intra cluster coherency 121 * --------------------------------------------- 122 */ 123 mov x30, x18 124 b cortex_a73_disable_smp 125endfunc cortex_a73_cluster_pwr_dwn 126 127func check_errata_cve_2017_5715 128 cpu_check_csv2 x0, 1f 129#if WORKAROUND_CVE_2017_5715 130 mov x0, #ERRATA_APPLIES 131#else 132 mov x0, #ERRATA_MISSING 133#endif 134 ret 1351: 136 mov x0, #ERRATA_NOT_APPLIES 137 ret 138endfunc check_errata_cve_2017_5715 139 140func check_errata_cve_2018_3639 141#if WORKAROUND_CVE_2018_3639 142 mov x0, #ERRATA_APPLIES 143#else 144 mov x0, #ERRATA_MISSING 145#endif 146 ret 147endfunc check_errata_cve_2018_3639 148 149#if REPORT_ERRATA 150/* 151 * Errata printing function for Cortex A75. Must follow AAPCS. 152 */ 153func cortex_a73_errata_report 154 stp x8, x30, [sp, #-16]! 155 156 bl cpu_get_rev_var 157 mov x8, x0 158 159 /* 160 * Report all errata. The revision-variant information is passed to 161 * checking functions of each errata. 162 */ 163 report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715 164 report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639 165 166 ldp x8, x30, [sp], #16 167 ret 168endfunc cortex_a73_errata_report 169#endif 170 171 /* --------------------------------------------- 172 * This function provides cortex_a73 specific 173 * register information for crash reporting. 174 * It needs to return with x6 pointing to 175 * a list of register names in ascii and 176 * x8 - x15 having values of registers to be 177 * reported. 178 * --------------------------------------------- 179 */ 180.section .rodata.cortex_a73_regs, "aS" 181cortex_a73_regs: /* The ascii list of register names to be reported */ 182 .asciz "cpuectlr_el1", "l2merrsr_el1", "" 183 184func cortex_a73_cpu_reg_dump 185 adr x6, cortex_a73_regs 186 mrs x8, CORTEX_A73_CPUECTLR_EL1 187 mrs x9, CORTEX_A73_L2MERRSR_EL1 188 ret 189endfunc cortex_a73_cpu_reg_dump 190 191declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \ 192 cortex_a73_reset_func, \ 193 check_errata_cve_2017_5715, \ 194 CPU_NO_EXTRA2_FUNC, \ 195 cortex_a73_core_pwr_dwn, \ 196 cortex_a73_cluster_pwr_dwn 197