1 /* 2 * Copyright (C) 2018 Marvell International Ltd. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * https://spdx.org/licenses 6 */ 7 8 /* AP807 Marvell SoC driver */ 9 10 #include <ap_setup.h> 11 #include <cache_llc.h> 12 #include <ccu.h> 13 #include <debug.h> 14 #include <io_win.h> 15 #include <mci.h> 16 #include <mmio.h> 17 #include <mvebu_def.h> 18 19 #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) 20 #define SMMU_sACR_PG_64K (1 << 16) 21 22 #define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 23 + 0x3F0) 24 #define GSPMU_CPU_CONTROL (0x1 << 0) 25 26 #define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ 27 + 0x200) 28 #define CCU_SET_POC_OFFSET 5 29 30 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) 31 #define DVM_48BIT_VA_ENABLE (1 << 21) 32 33 /* Secure MoChi incoming access */ 34 #define SEC_MOCHI_IN_ACC_REG (MVEBU_RFU_BASE + 0x4738) 35 #define SEC_MOCHI_IN_ACC_IHB0_EN (1) 36 #define SEC_MOCHI_IN_ACC_IHB1_EN (1 << 3) 37 #define SEC_MOCHI_IN_ACC_IHB2_EN (1 << 6) 38 #define SEC_MOCHI_IN_ACC_PIDI_EN (1 << 9) 39 #define SEC_IN_ACCESS_ENA_ALL_MASTERS (SEC_MOCHI_IN_ACC_IHB0_EN | \ 40 SEC_MOCHI_IN_ACC_IHB1_EN | \ 41 SEC_MOCHI_IN_ACC_IHB2_EN | \ 42 SEC_MOCHI_IN_ACC_PIDI_EN) 43 44 /* SYSRST_OUTn Config definitions */ 45 #define MVEBU_SYSRST_OUT_CONFIG_REG (MVEBU_MISC_SOC_BASE + 0x4) 46 #define WD_MASK_SYS_RST_OUT (1 << 2) 47 48 /* DSS PHY for DRAM */ 49 #define DSS_SCR_REG (MVEBU_RFU_BASE + 0x208) 50 #define DSS_PPROT_OFFS 4 51 #define DSS_PPROT_MASK 0x7 52 #define DSS_PPROT_PRIV_SECURE_DATA 0x1 53 54 /* Used for Units of AP-807 (e.g. SDIO and etc) */ 55 #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) 56 #define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ 57 0x4 * index) 58 59 enum axi_attr { 60 AXI_SDIO_ATTR = 0, 61 AXI_DFX_ATTR, 62 AXI_MAX_ATTR, 63 }; 64 65 static void ap_sec_masters_access_en(uint32_t enable) 66 { 67 uint32_t reg; 68 69 /* Open/Close incoming access for all masters. 70 * The access is disabled in trusted boot mode 71 * Could only be done in EL3 72 */ 73 reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); 74 if (enable) 75 mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | 76 SEC_IN_ACCESS_ENA_ALL_MASTERS); 77 else 78 mmio_write_32(SEC_MOCHI_IN_ACC_REG, 79 reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); 80 } 81 82 static void setup_smmu(void) 83 { 84 uint32_t reg; 85 86 /* Set the SMMU page size to 64 KB */ 87 reg = mmio_read_32(SMMU_sACR); 88 reg |= SMMU_sACR_PG_64K; 89 mmio_write_32(SMMU_sACR, reg); 90 } 91 92 static void init_aurora2(void) 93 { 94 uint32_t reg; 95 96 /* Enable GSPMU control by CPU */ 97 reg = mmio_read_32(CCU_GSPMU_CR); 98 reg |= GSPMU_CPU_CONTROL; 99 mmio_write_32(CCU_GSPMU_CR, reg); 100 101 #if LLC_ENABLE 102 /* Enable LLC for AP807 in exclusive mode */ 103 llc_enable(0, 1); 104 105 /* Set point of coherency to DDR. 106 * This is required by units which have 107 * SW cache coherency 108 */ 109 reg = mmio_read_32(CCU_HTC_CR); 110 reg |= (0x1 << CCU_SET_POC_OFFSET); 111 mmio_write_32(CCU_HTC_CR, reg); 112 #endif /* LLC_ENABLE */ 113 } 114 115 116 /* MCIx indirect access register are based by default at 0xf4000000/0xf6000000 117 * to avoid conflict of internal registers of units connected via MCIx, which 118 * can be based on the same address (i.e CP1 base is also 0xf4000000), 119 * the following routines remaps the MCIx indirect bases to another domain 120 */ 121 static void mci_remap_indirect_access_base(void) 122 { 123 uint32_t mci; 124 125 for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) 126 mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), 127 MVEBU_MCI_REG_BASE_REMAP(mci) >> 128 MCI_REMAP_OFF_SHIFT); 129 } 130 131 static void ap807_axi_attr_init(void) 132 { 133 uint32_t index, data; 134 135 /* Initialize AXI attributes for AP807 */ 136 /* Go over the AXI attributes and set Ax-Cache and Ax-Domain */ 137 for (index = 0; index < AXI_MAX_ATTR; index++) { 138 switch (index) { 139 /* DFX works with no coherent only - 140 * there's no option to configure the Ax-Cache and Ax-Domain 141 */ 142 case AXI_DFX_ATTR: 143 continue; 144 default: 145 /* Set Ax-Cache as cacheable, no allocate, modifiable, 146 * bufferable. 147 * The values are different because Read & Write 148 * definition is different in Ax-Cache 149 */ 150 data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); 151 data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; 152 data |= (CACHE_ATTR_WRITE_ALLOC | 153 CACHE_ATTR_CACHEABLE | 154 CACHE_ATTR_BUFFERABLE) << 155 MVEBU_AXI_ATTR_ARCACHE_OFFSET; 156 data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; 157 data |= (CACHE_ATTR_READ_ALLOC | 158 CACHE_ATTR_CACHEABLE | 159 CACHE_ATTR_BUFFERABLE) << 160 MVEBU_AXI_ATTR_AWCACHE_OFFSET; 161 /* Set Ax-Domain as Outer domain */ 162 data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; 163 data |= DOMAIN_OUTER_SHAREABLE << 164 MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; 165 data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; 166 data |= DOMAIN_OUTER_SHAREABLE << 167 MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; 168 mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); 169 } 170 } 171 } 172 173 static void misc_soc_configurations(void) 174 { 175 uint32_t reg; 176 177 /* Enable 48-bit VA */ 178 mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); 179 180 /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. 181 * Otherwise, upon WD timeout, the WD reset signal won't trigger reset 182 */ 183 reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); 184 reg &= ~(WD_MASK_SYS_RST_OUT); 185 mmio_write_32(MVEBU_SYSRST_OUT_CONFIG_REG, reg); 186 } 187 188 void ap_init(void) 189 { 190 /* Setup Aurora2. */ 191 init_aurora2(); 192 193 /* configure MCI mapping */ 194 mci_remap_indirect_access_base(); 195 196 /* configure IO_WIN windows */ 197 init_io_win(MVEBU_AP0); 198 199 /* configure CCU windows */ 200 init_ccu(MVEBU_AP0); 201 202 /* configure the SMMU */ 203 setup_smmu(); 204 205 /* Open AP incoming access for all masters */ 206 ap_sec_masters_access_en(1); 207 208 /* configure axi for AP */ 209 ap807_axi_attr_init(); 210 211 /* misc configuration of the SoC */ 212 misc_soc_configurations(); 213 } 214 215 static void ap807_dram_phy_access_config(void) 216 { 217 uint32_t reg_val; 218 /* Update DSS port access permission to DSS_PHY */ 219 reg_val = mmio_read_32(DSS_SCR_REG); 220 reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); 221 reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << 222 DSS_PPROT_OFFS); 223 mmio_write_32(DSS_SCR_REG, reg_val); 224 } 225 226 void ap_ble_init(void) 227 { 228 /* Enable DSS port */ 229 ap807_dram_phy_access_config(); 230 } 231 232 int ap_get_count(void) 233 { 234 return 1; 235 } 236 237 238