1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <platform_def.h> 12 13 #include <arch_helpers.h> 14 #include <bl1/tbbr/tbbr_img_desc.h> 15 #include <common/bl_common.h> 16 #include <common/debug.h> 17 #include <common/interrupt_props.h> 18 #include <drivers/arm/gicv2.h> 19 #include <drivers/arm/pl011.h> 20 #include <drivers/delay_timer.h> 21 #include <drivers/dw_ufs.h> 22 #include <drivers/generic_delay_timer.h> 23 #include <drivers/ufs.h> 24 #include <lib/mmio.h> 25 #include <plat/common/platform.h> 26 27 #include <hi3660.h> 28 #include "../../../bl1/bl1_private.h" 29 #include "hikey960_def.h" 30 #include "hikey960_private.h" 31 32 enum { 33 BOOT_MODE_RECOVERY = 0, 34 BOOT_MODE_NORMAL, 35 BOOT_MODE_MASK = 1, 36 }; 37 38 /* 39 * Declarations of linker defined symbols which will help us find the layout 40 * of trusted RAM 41 */ 42 43 /* Data structure which holds the extents of the trusted RAM for BL1 */ 44 static meminfo_t bl1_tzram_layout; 45 static console_pl011_t console; 46 47 /****************************************************************************** 48 * On a GICv2 system, the Group 1 secure interrupts are treated as Group 0 49 * interrupts. 50 *****************************************************************************/ 51 static const interrupt_prop_t g0_interrupt_props[] = { 52 INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, 53 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 54 INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, 55 GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL), 56 }; 57 58 const gicv2_driver_data_t hikey960_gic_data = { 59 .gicd_base = GICD_REG_BASE, 60 .gicc_base = GICC_REG_BASE, 61 .interrupt_props = g0_interrupt_props, 62 .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props), 63 }; 64 65 meminfo_t *bl1_plat_sec_mem_layout(void) 66 { 67 return &bl1_tzram_layout; 68 } 69 70 /* 71 * Perform any BL1 specific platform actions. 72 */ 73 void bl1_early_platform_setup(void) 74 { 75 unsigned int id, uart_base; 76 77 generic_delay_timer_init(); 78 hikey960_read_boardid(&id); 79 if (id == 5300) 80 uart_base = PL011_UART5_BASE; 81 else 82 uart_base = PL011_UART6_BASE; 83 /* Initialize the console to provide early debug support */ 84 console_pl011_register(uart_base, PL011_UART_CLK_IN_HZ, 85 PL011_BAUDRATE, &console); 86 87 /* Allow BL1 to see the whole Trusted RAM */ 88 bl1_tzram_layout.total_base = BL1_RW_BASE; 89 bl1_tzram_layout.total_size = BL1_RW_SIZE; 90 91 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 92 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 93 } 94 95 /* 96 * Perform the very early platform specific architecture setup here. At the 97 * moment this only does basic initialization. Later architectural setup 98 * (bl1_arch_setup()) does not do anything platform specific. 99 */ 100 void bl1_plat_arch_setup(void) 101 { 102 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, 103 bl1_tzram_layout.total_size, 104 BL1_RO_BASE, 105 BL1_RO_LIMIT, 106 BL_COHERENT_RAM_BASE, 107 BL_COHERENT_RAM_END); 108 } 109 110 static void hikey960_ufs_reset(void) 111 { 112 unsigned int data, mask; 113 114 mmio_write_32(CRG_PERDIS7_REG, 1 << 14); 115 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 116 do { 117 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 118 } while (data & BIT_SYSCTRL_REF_CLOCK_EN); 119 /* use abb clk */ 120 mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); 121 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); 122 mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); 123 mdelay(1); 124 mmio_write_32(CRG_PEREN7_REG, 1 << 14); 125 mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); 126 127 mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); 128 do { 129 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 130 } while ((data & PERI_UFS_BIT) == 0); 131 mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); 132 mdelay(1); 133 mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); 134 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 135 MASK_UFS_DEVICE_RESET); 136 /* clear SC_DIV_UFS_PERIBUS */ 137 mask = SC_DIV_UFS_PERIBUS << 16; 138 mmio_write_32(CRG_CLKDIV17_REG, mask); 139 /* set SC_DIV_UFSPHY_CFG(3) */ 140 mask = SC_DIV_UFSPHY_CFG_MASK << 16; 141 data = SC_DIV_UFSPHY_CFG(3); 142 mmio_write_32(CRG_CLKDIV16_REG, mask | data); 143 data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); 144 data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; 145 data |= 0x39; 146 mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); 147 mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); 148 mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, 149 MASK_UFS_CLK_GATE_BYPASS); 150 mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); 151 152 mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); 153 mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); 154 mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); 155 mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); 156 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); 157 mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); 158 mdelay(1); 159 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 160 MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); 161 mdelay(20); 162 mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 163 0x03300330); 164 165 mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); 166 do { 167 data = mmio_read_32(CRG_PERRSTSTAT3_REG); 168 } while (data & PERI_UFS_BIT); 169 } 170 171 static void hikey960_ufs_init(void) 172 { 173 dw_ufs_params_t ufs_params; 174 175 memset(&ufs_params, 0, sizeof(ufs_params)); 176 ufs_params.reg_base = UFS_REG_BASE; 177 ufs_params.desc_base = HIKEY960_UFS_DESC_BASE; 178 ufs_params.desc_size = HIKEY960_UFS_DESC_SIZE; 179 180 if ((ufs_params.flags & UFS_FLAGS_SKIPINIT) == 0) 181 hikey960_ufs_reset(); 182 dw_ufs_init(&ufs_params); 183 } 184 185 /* 186 * Function which will perform any remaining platform-specific setup that can 187 * occur after the MMU and data cache have been enabled. 188 */ 189 void bl1_platform_setup(void) 190 { 191 hikey960_clk_init(); 192 hikey960_pmu_init(); 193 hikey960_regulator_enable(); 194 hikey960_tzc_init(); 195 hikey960_peri_init(); 196 hikey960_ufs_init(); 197 hikey960_pinmux_init(); 198 hikey960_gpio_init(); 199 hikey960_io_setup(); 200 } 201 202 /* 203 * The following function checks if Firmware update is needed, 204 * by checking if TOC in FIP image is valid or not. 205 */ 206 unsigned int bl1_plat_get_next_image_id(void) 207 { 208 unsigned int mode, ret; 209 210 mode = mmio_read_32(SCTRL_BAK_DATA0_REG); 211 switch (mode & BOOT_MODE_MASK) { 212 case BOOT_MODE_RECOVERY: 213 ret = NS_BL1U_IMAGE_ID; 214 break; 215 default: 216 WARN("Invalid boot mode is found:%d\n", mode); 217 panic(); 218 } 219 return ret; 220 } 221 222 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 223 { 224 unsigned int index = 0; 225 226 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 227 if (bl1_tbbr_image_descs[index].image_id == image_id) 228 return &bl1_tbbr_image_descs[index]; 229 index++; 230 } 231 232 return NULL; 233 } 234 235 void bl1_plat_set_ep_info(unsigned int image_id, 236 entry_point_info_t *ep_info) 237 { 238 unsigned int data = 0; 239 uintptr_t tmp = HIKEY960_NS_TMP_OFFSET; 240 241 if (image_id != NS_BL1U_IMAGE_ID) 242 panic(); 243 /* Copy NS BL1U from 0x1AC1_8000 to 0x1AC9_8000 */ 244 memcpy((void *)tmp, (void *)HIKEY960_NS_IMAGE_OFFSET, 245 NS_BL1U_SIZE); 246 memcpy((void *)NS_BL1U_BASE, (void *)tmp, NS_BL1U_SIZE); 247 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 248 /* Initialize the GIC driver, cpu and distributor interfaces */ 249 gicv2_driver_init(&hikey960_gic_data); 250 gicv2_distif_init(); 251 gicv2_pcpu_distif_init(); 252 gicv2_cpuif_enable(); 253 /* CNTFRQ is read-only in EL1 */ 254 write_cntfrq_el0(plat_get_syscnt_freq2()); 255 data = read_cpacr_el1(); 256 do { 257 data |= 3 << 20; 258 write_cpacr_el1(data); 259 data = read_cpacr_el1(); 260 } while ((data & (3 << 20)) != (3 << 20)); 261 INFO("cpacr_el1:0x%x\n", data); 262 263 ep_info->args.arg0 = 0xffff & read_mpidr(); 264 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 265 DISABLE_ALL_EXCEPTIONS); 266 } 267