1/* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <cortex_a75.h> 10#include <cpuamu.h> 11#include <cpu_macros.S> 12 13func cortex_a75_reset_func 14 mov x19, x30 15#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 16 cpu_check_csv2 x0, 1f 17 adr x0, wa_cve_2017_5715_bpiall_vbar 18 msr vbar_el3, x0 19 isb 201: 21#endif 22 23#if WORKAROUND_CVE_2018_3639 24 mrs x0, CORTEX_A75_CPUACTLR_EL1 25 orr x0, x0, #CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE 26 msr CORTEX_A75_CPUACTLR_EL1, x0 27 isb 28#endif 29 30#if ERRATA_DSU_936184 31 bl errata_dsu_936184_wa 32#endif 33 34#if ENABLE_AMU 35 /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ 36 mrs x0, actlr_el3 37 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 38 msr actlr_el3, x0 39 isb 40 41 /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ 42 mrs x0, actlr_el2 43 orr x0, x0, #CORTEX_A75_ACTLR_AMEN_BIT 44 msr actlr_el2, x0 45 isb 46 47 /* Enable group0 counters */ 48 mov x0, #CORTEX_A75_AMU_GROUP0_MASK 49 msr CPUAMCNTENSET_EL0, x0 50 isb 51 52 /* Enable group1 counters */ 53 mov x0, #CORTEX_A75_AMU_GROUP1_MASK 54 msr CPUAMCNTENSET_EL0, x0 55 isb 56#endif 57 ret x19 58endfunc cortex_a75_reset_func 59 60func check_errata_cve_2017_5715 61 cpu_check_csv2 x0, 1f 62#if WORKAROUND_CVE_2017_5715 63 mov x0, #ERRATA_APPLIES 64#else 65 mov x0, #ERRATA_MISSING 66#endif 67 ret 681: 69 mov x0, #ERRATA_NOT_APPLIES 70 ret 71endfunc check_errata_cve_2017_5715 72 73func check_errata_cve_2018_3639 74#if WORKAROUND_CVE_2018_3639 75 mov x0, #ERRATA_APPLIES 76#else 77 mov x0, #ERRATA_MISSING 78#endif 79 ret 80endfunc check_errata_cve_2018_3639 81 82 /* --------------------------------------------- 83 * HW will do the cache maintenance while powering down 84 * --------------------------------------------- 85 */ 86func cortex_a75_core_pwr_dwn 87 /* --------------------------------------------- 88 * Enable CPU power down bit in power control register 89 * --------------------------------------------- 90 */ 91 mrs x0, CORTEX_A75_CPUPWRCTLR_EL1 92 orr x0, x0, #CORTEX_A75_CORE_PWRDN_EN_MASK 93 msr CORTEX_A75_CPUPWRCTLR_EL1, x0 94 isb 95 ret 96endfunc cortex_a75_core_pwr_dwn 97 98#if REPORT_ERRATA 99/* 100 * Errata printing function for Cortex A75. Must follow AAPCS. 101 */ 102func cortex_a75_errata_report 103 stp x8, x30, [sp, #-16]! 104 105 bl cpu_get_rev_var 106 mov x8, x0 107 108 /* 109 * Report all errata. The revision-variant information is passed to 110 * checking functions of each errata. 111 */ 112 report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715 113 report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639 114 report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184 115 116 ldp x8, x30, [sp], #16 117 ret 118endfunc cortex_a75_errata_report 119#endif 120 121 /* --------------------------------------------- 122 * This function provides cortex_a75 specific 123 * register information for crash reporting. 124 * It needs to return with x6 pointing to 125 * a list of register names in ascii and 126 * x8 - x15 having values of registers to be 127 * reported. 128 * --------------------------------------------- 129 */ 130.section .rodata.cortex_a75_regs, "aS" 131cortex_a75_regs: /* The ascii list of register names to be reported */ 132 .asciz "cpuectlr_el1", "" 133 134func cortex_a75_cpu_reg_dump 135 adr x6, cortex_a75_regs 136 mrs x8, CORTEX_A75_CPUECTLR_EL1 137 ret 138endfunc cortex_a75_cpu_reg_dump 139 140declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ 141 cortex_a75_reset_func, \ 142 check_errata_cve_2017_5715, \ 143 CPU_NO_EXTRA2_FUNC, \ 144 cortex_a75_core_pwr_dwn 145