1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 10 #include <arch.h> 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/runtime_svc.h> 15 #include <denver.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 18 #include <mce.h> 19 #include <memctrl.h> 20 #include <t18x_ari.h> 21 #include <tegra_private.h> 22 23 extern uint32_t tegra186_system_powerdn_state; 24 25 /******************************************************************************* 26 * Offset to read the ref_clk counter value 27 ******************************************************************************/ 28 #define REF_CLK_OFFSET 4 29 30 /******************************************************************************* 31 * Tegra186 SiP SMCs 32 ******************************************************************************/ 33 #define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01 34 #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 35 #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 36 #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 37 #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 38 #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 39 #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 40 #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 41 #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06 42 #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 43 #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 44 #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 45 #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A 46 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B 47 #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C 48 #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D 49 #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E 50 #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F 51 #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 52 #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 53 #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 54 55 /******************************************************************************* 56 * This function is responsible for handling all T186 SiP calls 57 ******************************************************************************/ 58 int plat_sip_handler(uint32_t smc_fid, 59 uint64_t x1, 60 uint64_t x2, 61 uint64_t x3, 62 uint64_t x4, 63 void *cookie, 64 void *handle, 65 uint64_t flags) 66 { 67 int mce_ret; 68 int impl, cpu; 69 uint32_t base, core_clk_ctr, ref_clk_ctr; 70 71 if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { 72 /* 32-bit function, clear top parameter bits */ 73 74 x1 = (uint32_t)x1; 75 x2 = (uint32_t)x2; 76 x3 = (uint32_t)x3; 77 } 78 79 /* 80 * Convert SMC FID to SMC64, to support SMC32/SMC64 configurations 81 */ 82 smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); 83 84 switch (smc_fid) { 85 /* 86 * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - 87 * 0x82FFFFFF SiP SMC space 88 */ 89 case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: 90 case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: 91 case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: 92 case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: 93 case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: 94 case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: 95 case TEGRA_SIP_MCE_CMD_CC3_CTRL: 96 case TEGRA_SIP_MCE_CMD_ECHO_DATA: 97 case TEGRA_SIP_MCE_CMD_READ_VERSIONS: 98 case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: 99 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: 100 case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: 101 case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: 102 case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: 103 case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: 104 case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: 105 case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: 106 case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: 107 108 /* clean up the high bits */ 109 smc_fid &= MCE_CMD_MASK; 110 111 /* execute the command and store the result */ 112 mce_ret = mce_command_handler(smc_fid, x1, x2, x3); 113 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, 114 (uint64_t)mce_ret); 115 116 return 0; 117 118 case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE: 119 120 /* clean up the high bits */ 121 x1 = (uint32_t)x1; 122 123 /* 124 * SC8 is a special Tegra186 system state where the CPUs and 125 * DRAM are powered down but the other subsystem is still 126 * alive. 127 */ 128 if ((x1 == TEGRA_ARI_SYSTEM_SC8) || 129 (x1 == TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF)) { 130 131 tegra186_system_powerdn_state = x1; 132 flush_dcache_range( 133 (uintptr_t)&tegra186_system_powerdn_state, 134 sizeof(tegra186_system_powerdn_state)); 135 136 } else { 137 138 ERROR("%s: unhandled powerdn state (%d)\n", __func__, 139 (uint32_t)x1); 140 return -ENOTSUP; 141 } 142 143 return 0; 144 145 /* 146 * This function ID reads the Activity monitor's core/ref clock 147 * counter values for a core/cluster. 148 * 149 * x1 = MPIDR of the target core 150 * x2 = MIDR of the target core 151 */ 152 case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS: 153 154 cpu = (uint32_t)x1 & MPIDR_CPU_MASK; 155 impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; 156 157 /* sanity check target CPU number */ 158 if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER) 159 return -EINVAL; 160 161 /* get the base address for the current CPU */ 162 base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE : 163 TEGRA_ARM_ACTMON_CTR_BASE; 164 165 /* read the clock counter values */ 166 core_clk_ctr = mmio_read_32(base + (8 * cpu)); 167 ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET); 168 169 /* return the counter values as two different parameters */ 170 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, 171 (uint64_t)core_clk_ctr); 172 write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, 173 (uint64_t)ref_clk_ctr); 174 175 return 0; 176 177 default: 178 break; 179 } 180 181 return -ENOTSUP; 182 } 183