1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <bl1/tbbr/tbbr_img_desc.h> 13 #include <common/bl_common.h> 14 #include <common/debug.h> 15 #include <drivers/arm/pl011.h> 16 #include <drivers/mmc.h> 17 #include <drivers/synopsys/dw_mmc.h> 18 #include <lib/mmio.h> 19 #include <plat/common/platform.h> 20 21 #include <hi6220.h> 22 #include <hikey_def.h> 23 #include <hikey_layout.h> 24 25 #include "../../../bl1/bl1_private.h" 26 #include "hikey_private.h" 27 28 /* Data structure which holds the extents of the trusted RAM for BL1 */ 29 static meminfo_t bl1_tzram_layout; 30 static console_pl011_t console; 31 32 enum { 33 BOOT_NORMAL = 0, 34 BOOT_USB_DOWNLOAD, 35 BOOT_UART_DOWNLOAD, 36 }; 37 38 meminfo_t *bl1_plat_sec_mem_layout(void) 39 { 40 return &bl1_tzram_layout; 41 } 42 43 /* 44 * Perform any BL1 specific platform actions. 45 */ 46 void bl1_early_platform_setup(void) 47 { 48 /* Initialize the console to provide early debug support */ 49 console_pl011_register(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, 50 PL011_BAUDRATE, &console); 51 52 /* Allow BL1 to see the whole Trusted RAM */ 53 bl1_tzram_layout.total_base = BL1_RW_BASE; 54 bl1_tzram_layout.total_size = BL1_RW_SIZE; 55 56 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 57 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 58 } 59 60 /* 61 * Perform the very early platform specific architecture setup here. At the 62 * moment this only does basic initialization. Later architectural setup 63 * (bl1_arch_setup()) does not do anything platform specific. 64 */ 65 void bl1_plat_arch_setup(void) 66 { 67 hikey_init_mmu_el3(bl1_tzram_layout.total_base, 68 bl1_tzram_layout.total_size, 69 BL1_RO_BASE, 70 BL1_RO_LIMIT, 71 BL_COHERENT_RAM_BASE, 72 BL_COHERENT_RAM_END); 73 } 74 75 /* 76 * Function which will perform any remaining platform-specific setup that can 77 * occur after the MMU and data cache have been enabled. 78 */ 79 void bl1_platform_setup(void) 80 { 81 dw_mmc_params_t params; 82 struct mmc_device_info info; 83 84 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && 85 ((SRAM_BASE + SRAM_SIZE) >= 86 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE))); 87 hikey_sp804_init(); 88 hikey_gpio_init(); 89 hikey_pmussi_init(); 90 hikey_hi6553_init(); 91 92 hikey_rtc_init(); 93 94 hikey_mmc_pll_init(); 95 96 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 97 params.reg_base = DWMMC0_BASE; 98 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; 99 params.desc_size = 1 << 20; 100 params.clk_rate = 24 * 1000 * 1000; 101 params.bus_width = MMC_BUS_WIDTH_8; 102 params.flags = MMC_FLAG_CMD23; 103 info.mmc_dev_type = MMC_IS_EMMC; 104 dw_mmc_init(¶ms, &info); 105 106 hikey_io_setup(); 107 } 108 109 /* 110 * The following function checks if Firmware update is needed, 111 * by checking if TOC in FIP image is valid or not. 112 */ 113 unsigned int bl1_plat_get_next_image_id(void) 114 { 115 int32_t boot_mode; 116 unsigned int ret; 117 118 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 119 switch (boot_mode) { 120 case BOOT_USB_DOWNLOAD: 121 case BOOT_UART_DOWNLOAD: 122 ret = NS_BL1U_IMAGE_ID; 123 break; 124 default: 125 WARN("Invalid boot mode is found:%d\n", boot_mode); 126 panic(); 127 } 128 return ret; 129 } 130 131 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 132 { 133 unsigned int index = 0; 134 135 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 136 if (bl1_tbbr_image_descs[index].image_id == image_id) 137 return &bl1_tbbr_image_descs[index]; 138 139 index++; 140 } 141 142 return NULL; 143 } 144 145 void bl1_plat_set_ep_info(unsigned int image_id, 146 entry_point_info_t *ep_info) 147 { 148 uint64_t data = 0; 149 150 if (image_id == BL2_IMAGE_ID) 151 panic(); 152 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 153 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 154 do { 155 data |= 3 << 20; 156 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data)); 157 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 158 } while ((data & (3 << 20)) != (3 << 20)); 159 INFO("cpacr_el1:0x%llx\n", data); 160 161 ep_info->args.arg0 = 0xffff & read_mpidr(); 162 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 163 DISABLE_ALL_EXCEPTIONS); 164 } 165