1 /* 2 * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <mce.h> 10 #include <mmio.h> 11 #include <string.h> 12 #include <tegra_def.h> 13 #include <tegra_private.h> 14 15 #define MISCREG_CPU_RESET_VECTOR 0x2000 16 #define MISCREG_AA64_RST_LOW 0x2004 17 #define MISCREG_AA64_RST_HIGH 0x2008 18 19 #define SCRATCH_SECURE_RSV1_SCRATCH_0 0x658 20 #define SCRATCH_SECURE_RSV1_SCRATCH_1 0x65C 21 22 #define CPU_RESET_MODE_AA64 1 23 24 extern void memcpy16(void *dest, const void *src, unsigned int length); 25 26 extern uint64_t tegra_bl31_phys_base; 27 extern uint64_t __tegra186_cpu_reset_handler_end; 28 29 /******************************************************************************* 30 * Setup secondary CPU vectors 31 ******************************************************************************/ 32 void plat_secondary_setup(void) 33 { 34 uint32_t addr_low, addr_high; 35 plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); 36 uint64_t cpu_reset_handler_base; 37 38 INFO("Setting up secondary CPU boot\n"); 39 40 if ((tegra_bl31_phys_base >= TEGRA_TZRAM_BASE) && 41 (tegra_bl31_phys_base <= (TEGRA_TZRAM_BASE + TEGRA_TZRAM_SIZE))) { 42 43 /* 44 * The BL31 code resides in the TZSRAM which loses state 45 * when we enter System Suspend. Copy the wakeup trampoline 46 * code to TZDRAM to help us exit from System Suspend. 47 */ 48 cpu_reset_handler_base = params_from_bl2->tzdram_base; 49 memcpy16((void *)((uintptr_t)cpu_reset_handler_base), 50 (void *)(uintptr_t)tegra186_cpu_reset_handler, 51 (uintptr_t)&__tegra186_cpu_reset_handler_end - 52 (uintptr_t)tegra186_cpu_reset_handler); 53 54 } else { 55 cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint; 56 } 57 58 addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64; 59 addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff); 60 61 /* write lower 32 bits first, then the upper 11 bits */ 62 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low); 63 mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high); 64 65 /* save reset vector to be used during SYSTEM_SUSPEND exit */ 66 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_0, 67 addr_low); 68 mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_RSV1_SCRATCH_1, 69 addr_high); 70 71 /* update reset vector address to the CCPLEX */ 72 mce_update_reset_vector(); 73 } 74