1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __GICV3_H__ 8 #define __GICV3_H__ 9 10 /******************************************************************************* 11 * GICv3 miscellaneous definitions 12 ******************************************************************************/ 13 /* Interrupt group definitions */ 14 #define INTR_GROUP1S 0 15 #define INTR_GROUP0 1 16 #define INTR_GROUP1NS 2 17 18 /* Interrupt IDs reported by the HPPIR and IAR registers */ 19 #define PENDING_G1S_INTID 1020 20 #define PENDING_G1NS_INTID 1021 21 22 /* Constant to categorize LPI interrupt */ 23 #define MIN_LPI_ID 8192 24 25 /******************************************************************************* 26 * GICv3 specific Distributor interface register offsets and constants. 27 ******************************************************************************/ 28 #define GICD_STATUSR 0x10 29 #define GICD_SETSPI_NSR 0x40 30 #define GICD_CLRSPI_NSR 0x48 31 #define GICD_SETSPI_SR 0x50 32 #define GICD_CLRSPI_SR 0x50 33 #define GICD_IGRPMODR 0xd00 34 /* 35 * GICD_IROUTER<n> register is at 0x6000 + 8n, where n is the interrupt id and 36 * n >= 32, making the effective offset as 0x6100. 37 */ 38 #define GICD_IROUTER 0x6000 39 #define GICD_PIDR2_GICV3 0xffe8 40 41 #define IGRPMODR_SHIFT 5 42 43 /* GICD_CTLR bit definitions */ 44 #define CTLR_ENABLE_G1NS_SHIFT 1 45 #define CTLR_ENABLE_G1S_SHIFT 2 46 #define CTLR_ARE_S_SHIFT 4 47 #define CTLR_ARE_NS_SHIFT 5 48 #define CTLR_DS_SHIFT 6 49 #define CTLR_E1NWF_SHIFT 7 50 #define GICD_CTLR_RWP_SHIFT 31 51 52 #define CTLR_ENABLE_G1NS_MASK 0x1 53 #define CTLR_ENABLE_G1S_MASK 0x1 54 #define CTLR_ARE_S_MASK 0x1 55 #define CTLR_ARE_NS_MASK 0x1 56 #define CTLR_DS_MASK 0x1 57 #define CTLR_E1NWF_MASK 0x1 58 #define GICD_CTLR_RWP_MASK 0x1 59 60 #define CTLR_ENABLE_G1NS_BIT (1 << CTLR_ENABLE_G1NS_SHIFT) 61 #define CTLR_ENABLE_G1S_BIT (1 << CTLR_ENABLE_G1S_SHIFT) 62 #define CTLR_ARE_S_BIT (1 << CTLR_ARE_S_SHIFT) 63 #define CTLR_ARE_NS_BIT (1 << CTLR_ARE_NS_SHIFT) 64 #define CTLR_DS_BIT (1 << CTLR_DS_SHIFT) 65 #define CTLR_E1NWF_BIT (1 << CTLR_E1NWF_SHIFT) 66 #define GICD_CTLR_RWP_BIT (1 << GICD_CTLR_RWP_SHIFT) 67 68 /* GICD_IROUTER shifts and masks */ 69 #define IROUTER_IRM_SHIFT 31 70 #define IROUTER_IRM_MASK 0x1 71 72 /******************************************************************************* 73 * GICv3 Re-distributor interface registers & constants 74 ******************************************************************************/ 75 #define GICR_PCPUBASE_SHIFT 0x11 76 #define GICR_SGIBASE_OFFSET (1 << 0x10) /* 64 KB */ 77 #define GICR_CTLR 0x0 78 #define GICR_TYPER 0x08 79 #define GICR_WAKER 0x14 80 #define GICR_IGROUPR0 (GICR_SGIBASE_OFFSET + 0x80) 81 #define GICR_ISENABLER0 (GICR_SGIBASE_OFFSET + 0x100) 82 #define GICR_ICENABLER0 (GICR_SGIBASE_OFFSET + 0x180) 83 #define GICR_IPRIORITYR (GICR_SGIBASE_OFFSET + 0x400) 84 #define GICR_ICFGR0 (GICR_SGIBASE_OFFSET + 0xc00) 85 #define GICR_ICFGR1 (GICR_SGIBASE_OFFSET + 0xc04) 86 #define GICR_IGRPMODR0 (GICR_SGIBASE_OFFSET + 0xd00) 87 88 /* GICR_CTLR bit definitions */ 89 #define GICR_CTLR_RWP_SHIFT 3 90 #define GICR_CTLR_RWP_MASK 0x1 91 #define GICR_CTLR_RWP_BIT (1 << GICR_CTLR_RWP_SHIFT) 92 93 /* GICR_WAKER bit definitions */ 94 #define WAKER_CA_SHIFT 2 95 #define WAKER_PS_SHIFT 1 96 97 #define WAKER_CA_MASK 0x1 98 #define WAKER_PS_MASK 0x1 99 100 #define WAKER_CA_BIT (1 << WAKER_CA_SHIFT) 101 #define WAKER_PS_BIT (1 << WAKER_PS_SHIFT) 102 103 /* GICR_TYPER bit definitions */ 104 #define TYPER_AFF_VAL_SHIFT 32 105 #define TYPER_PROC_NUM_SHIFT 8 106 #define TYPER_LAST_SHIFT 4 107 108 #define TYPER_AFF_VAL_MASK 0xffffffff 109 #define TYPER_PROC_NUM_MASK 0xffff 110 #define TYPER_LAST_MASK 0x1 111 112 #define TYPER_LAST_BIT (1 << TYPER_LAST_SHIFT) 113 114 /******************************************************************************* 115 * GICv3 CPU interface registers & constants 116 ******************************************************************************/ 117 /* ICC_SRE bit definitions*/ 118 #define ICC_SRE_EN_BIT (1 << 3) 119 #define ICC_SRE_DIB_BIT (1 << 2) 120 #define ICC_SRE_DFB_BIT (1 << 1) 121 #define ICC_SRE_SRE_BIT (1 << 0) 122 123 /* ICC_IGRPEN1_EL3 bit definitions */ 124 #define IGRPEN1_EL3_ENABLE_G1NS_SHIFT 0 125 #define IGRPEN1_EL3_ENABLE_G1S_SHIFT 1 126 127 #define IGRPEN1_EL3_ENABLE_G1NS_BIT (1 << IGRPEN1_EL3_ENABLE_G1NS_SHIFT) 128 #define IGRPEN1_EL3_ENABLE_G1S_BIT (1 << IGRPEN1_EL3_ENABLE_G1S_SHIFT) 129 130 /* ICC_IGRPEN0_EL1 bit definitions */ 131 #define IGRPEN1_EL1_ENABLE_G0_SHIFT 0 132 #define IGRPEN1_EL1_ENABLE_G0_BIT (1 << IGRPEN1_EL1_ENABLE_G0_SHIFT) 133 134 /* ICC_HPPIR0_EL1 bit definitions */ 135 #define HPPIR0_EL1_INTID_SHIFT 0 136 #define HPPIR0_EL1_INTID_MASK 0xffffff 137 138 /* ICC_HPPIR1_EL1 bit definitions */ 139 #define HPPIR1_EL1_INTID_SHIFT 0 140 #define HPPIR1_EL1_INTID_MASK 0xffffff 141 142 /* ICC_IAR0_EL1 bit definitions */ 143 #define IAR0_EL1_INTID_SHIFT 0 144 #define IAR0_EL1_INTID_MASK 0xffffff 145 146 /* ICC_IAR1_EL1 bit definitions */ 147 #define IAR1_EL1_INTID_SHIFT 0 148 #define IAR1_EL1_INTID_MASK 0xffffff 149 150 #ifndef __ASSEMBLY__ 151 152 #include <stdint.h> 153 #include <types.h> 154 155 #define gicv3_is_intr_id_special_identifier(id) \ 156 (((id) >= PENDING_G1S_INTID) && ((id) <= GIC_SPURIOUS_INTERRUPT)) 157 158 /******************************************************************************* 159 * Helper GICv3 macros for SEL1 160 ******************************************************************************/ 161 #define gicv3_acknowledge_interrupt_sel1() read_icc_iar1_el1() &\ 162 IAR1_EL1_INTID_MASK 163 #define gicv3_get_pending_interrupt_id_sel1() read_icc_hppir1_el1() &\ 164 HPPIR1_EL1_INTID_MASK 165 #define gicv3_end_of_interrupt_sel1(id) write_icc_eoir1_el1(id) 166 167 168 /******************************************************************************* 169 * Helper GICv3 macros for EL3 170 ******************************************************************************/ 171 #define gicv3_acknowledge_interrupt() read_icc_iar0_el1() &\ 172 IAR0_EL1_INTID_MASK 173 #define gicv3_end_of_interrupt(id) write_icc_eoir0_el1(id) 174 175 /******************************************************************************* 176 * This structure describes some of the implementation defined attributes of the 177 * GICv3 IP. It is used by the platform port to specify these attributes in order 178 * to initialise the GICV3 driver. The attributes are described below. 179 * 180 * 1. The 'gicd_base' field contains the base address of the Distributor 181 * interface programmer's view. 182 * 183 * 2. The 'gicr_base' field contains the base address of the Re-distributor 184 * interface programmer's view. 185 * 186 * 3. The 'g0_interrupt_array' field is a ponter to an array in which each 187 * entry corresponds to an ID of a Group 0 interrupt. 188 * 189 * 4. The 'g0_interrupt_num' field contains the number of entries in the 190 * 'g0_interrupt_array'. 191 * 192 * 5. The 'g1s_interrupt_array' field is a ponter to an array in which each 193 * entry corresponds to an ID of a Group 1 interrupt. 194 * 195 * 6. The 'g1s_interrupt_num' field contains the number of entries in the 196 * 'g1s_interrupt_array'. 197 * 198 * 7. The 'rdistif_num' field contains the number of Redistributor interfaces 199 * the GIC implements. This is equal to the number of CPUs or CPU interfaces 200 * instantiated in the GIC. 201 * 202 * 8. The 'rdistif_base_addrs' field is a pointer to an array that has an entry 203 * for storing the base address of the Redistributor interface frame of each 204 * CPU in the system. The size of the array = 'rdistif_num'. The base 205 * addresses are detected during driver initialisation. 206 * 207 * 9. The 'mpidr_to_core_pos' field is a pointer to a hash function which the 208 * driver will use to convert an MPIDR value to a linear core index. This 209 * index will be used for accessing the 'rdistif_base_addrs' array. This is 210 * an optional field. A GICv3 implementation maps each MPIDR to a linear core 211 * index as well. This mapping can be found by reading the "Affinity Value" 212 * and "Processor Number" fields in the GICR_TYPER. It is IMP. DEF. if the 213 * "Processor Numbers" are suitable to index into an array to access core 214 * specific information. If this not the case, the platform port must provide 215 * a hash function. Otherwise, the "Processor Number" field will be used to 216 * access the array elements. 217 ******************************************************************************/ 218 typedef unsigned int (*mpidr_hash_fn)(u_register_t mpidr); 219 220 typedef struct gicv3_driver_data { 221 uintptr_t gicd_base; 222 uintptr_t gicr_base; 223 unsigned int g0_interrupt_num; 224 unsigned int g1s_interrupt_num; 225 const unsigned int *g0_interrupt_array; 226 const unsigned int *g1s_interrupt_array; 227 unsigned int rdistif_num; 228 uintptr_t *rdistif_base_addrs; 229 mpidr_hash_fn mpidr_to_core_pos; 230 } gicv3_driver_data_t; 231 232 /******************************************************************************* 233 * GICv3 EL3 driver API 234 ******************************************************************************/ 235 void gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data); 236 void gicv3_distif_init(void); 237 void gicv3_rdistif_init(unsigned int proc_num); 238 void gicv3_rdistif_on(unsigned int proc_num); 239 void gicv3_rdistif_off(unsigned int proc_num); 240 void gicv3_cpuif_enable(unsigned int proc_num); 241 void gicv3_cpuif_disable(unsigned int proc_num); 242 unsigned int gicv3_get_pending_interrupt_type(void); 243 unsigned int gicv3_get_pending_interrupt_id(void); 244 unsigned int gicv3_get_interrupt_type(unsigned int id, 245 unsigned int proc_num); 246 247 248 #endif /* __ASSEMBLY__ */ 249 #endif /* __GICV3_H__ */ 250