1/* 2 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <context.h> 10#include <cpu_data.h> 11#include <ea_handle.h> 12#include <interrupt_mgmt.h> 13#include <platform_def.h> 14#include <runtime_svc.h> 15#include <smccc.h> 16 17 .globl runtime_exceptions 18 19 .globl sync_exception_sp_el0 20 .globl irq_sp_el0 21 .globl fiq_sp_el0 22 .globl serror_sp_el0 23 24 .globl sync_exception_sp_elx 25 .globl irq_sp_elx 26 .globl fiq_sp_elx 27 .globl serror_sp_elx 28 29 .globl sync_exception_aarch64 30 .globl irq_aarch64 31 .globl fiq_aarch64 32 .globl serror_aarch64 33 34 .globl sync_exception_aarch32 35 .globl irq_aarch32 36 .globl fiq_aarch32 37 .globl serror_aarch32 38 39 /* 40 * Macro that prepares entry to EL3 upon taking an exception. 41 * 42 * With RAS_EXTENSION, this macro synchronizes pending errors with an ESB 43 * instruction. When an error is thus synchronized, the handling is 44 * delegated to platform EA handler. 45 * 46 * Without RAS_EXTENSION, this macro just saves x30, and unmasks 47 * Asynchronous External Aborts. 48 */ 49 .macro check_and_unmask_ea 50#if RAS_EXTENSION 51 /* Synchronize pending External Aborts */ 52 esb 53 54 /* Unmask the SError interrupt */ 55 msr daifclr, #DAIF_ABT_BIT 56 57 /* 58 * Explicitly save x30 so as to free up a register and to enable 59 * branching 60 */ 61 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 62 63 /* Check for SErrors synchronized by the ESB instruction */ 64 mrs x30, DISR_EL1 65 tbz x30, #DISR_A_BIT, 1f 66 67 /* Save GP registers and restore them afterwards */ 68 bl save_gp_registers 69 bl handle_lower_el_ea_esb 70 bl restore_gp_registers 71 721: 73#else 74 /* Unmask the SError interrupt */ 75 msr daifclr, #DAIF_ABT_BIT 76 77 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 78#endif 79 .endm 80 81 /* --------------------------------------------------------------------- 82 * This macro handles Synchronous exceptions. 83 * Only SMC exceptions are supported. 84 * --------------------------------------------------------------------- 85 */ 86 .macro handle_sync_exception 87#if ENABLE_RUNTIME_INSTRUMENTATION 88 /* 89 * Read the timestamp value and store it in per-cpu data. The value 90 * will be extracted from per-cpu data by the C level SMC handler and 91 * saved to the PMF timestamp region. 92 */ 93 mrs x30, cntpct_el0 94 str x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 95 mrs x29, tpidr_el3 96 str x30, [x29, #CPU_DATA_PMF_TS0_OFFSET] 97 ldr x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X29] 98#endif 99 100 mrs x30, esr_el3 101 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH 102 103 /* Handle SMC exceptions separately from other synchronous exceptions */ 104 cmp x30, #EC_AARCH32_SMC 105 b.eq smc_handler32 106 107 cmp x30, #EC_AARCH64_SMC 108 b.eq smc_handler64 109 110 /* Synchronous exceptions other than the above are assumed to be EA */ 111 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 112 b enter_lower_el_sync_ea 113 .endm 114 115 116 /* --------------------------------------------------------------------- 117 * This macro handles FIQ or IRQ interrupts i.e. EL3, S-EL1 and NS 118 * interrupts. 119 * --------------------------------------------------------------------- 120 */ 121 .macro handle_interrupt_exception label 122 bl save_gp_registers 123 /* Save the EL3 system registers needed to return from this exception */ 124 mrs x0, spsr_el3 125 mrs x1, elr_el3 126 stp x0, x1, [sp, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 127 128 /* Switch to the runtime stack i.e. SP_EL0 */ 129 ldr x2, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 130 mov x20, sp 131 msr spsel, #0 132 mov sp, x2 133 134 /* 135 * Find out whether this is a valid interrupt type. 136 * If the interrupt controller reports a spurious interrupt then return 137 * to where we came from. 138 */ 139 bl plat_ic_get_pending_interrupt_type 140 cmp x0, #INTR_TYPE_INVAL 141 b.eq interrupt_exit_\label 142 143 /* 144 * Get the registered handler for this interrupt type. 145 * A NULL return value could be 'cause of the following conditions: 146 * 147 * a. An interrupt of a type was routed correctly but a handler for its 148 * type was not registered. 149 * 150 * b. An interrupt of a type was not routed correctly so a handler for 151 * its type was not registered. 152 * 153 * c. An interrupt of a type was routed correctly to EL3, but was 154 * deasserted before its pending state could be read. Another 155 * interrupt of a different type pended at the same time and its 156 * type was reported as pending instead. However, a handler for this 157 * type was not registered. 158 * 159 * a. and b. can only happen due to a programming error. The 160 * occurrence of c. could be beyond the control of Trusted Firmware. 161 * It makes sense to return from this exception instead of reporting an 162 * error. 163 */ 164 bl get_interrupt_type_handler 165 cbz x0, interrupt_exit_\label 166 mov x21, x0 167 168 mov x0, #INTR_ID_UNAVAILABLE 169 170 /* Set the current security state in the 'flags' parameter */ 171 mrs x2, scr_el3 172 ubfx x1, x2, #0, #1 173 174 /* Restore the reference to the 'handle' i.e. SP_EL3 */ 175 mov x2, x20 176 177 /* x3 will point to a cookie (not used now) */ 178 mov x3, xzr 179 180 /* Call the interrupt type handler */ 181 blr x21 182 183interrupt_exit_\label: 184 /* Return from exception, possibly in a different security state */ 185 b el3_exit 186 187 .endm 188 189 190vector_base runtime_exceptions 191 192 /* --------------------------------------------------------------------- 193 * Current EL with SP_EL0 : 0x0 - 0x200 194 * --------------------------------------------------------------------- 195 */ 196vector_entry sync_exception_sp_el0 197 /* We don't expect any synchronous exceptions from EL3 */ 198 b report_unhandled_exception 199end_vector_entry sync_exception_sp_el0 200 201vector_entry irq_sp_el0 202 /* 203 * EL3 code is non-reentrant. Any asynchronous exception is a serious 204 * error. Loop infinitely. 205 */ 206 b report_unhandled_interrupt 207end_vector_entry irq_sp_el0 208 209 210vector_entry fiq_sp_el0 211 b report_unhandled_interrupt 212end_vector_entry fiq_sp_el0 213 214 215vector_entry serror_sp_el0 216 no_ret plat_handle_el3_ea 217end_vector_entry serror_sp_el0 218 219 /* --------------------------------------------------------------------- 220 * Current EL with SP_ELx: 0x200 - 0x400 221 * --------------------------------------------------------------------- 222 */ 223vector_entry sync_exception_sp_elx 224 /* 225 * This exception will trigger if anything went wrong during a previous 226 * exception entry or exit or while handling an earlier unexpected 227 * synchronous exception. There is a high probability that SP_EL3 is 228 * corrupted. 229 */ 230 b report_unhandled_exception 231end_vector_entry sync_exception_sp_elx 232 233vector_entry irq_sp_elx 234 b report_unhandled_interrupt 235end_vector_entry irq_sp_elx 236 237vector_entry fiq_sp_elx 238 b report_unhandled_interrupt 239end_vector_entry fiq_sp_elx 240 241vector_entry serror_sp_elx 242 no_ret plat_handle_el3_ea 243end_vector_entry serror_sp_elx 244 245 /* --------------------------------------------------------------------- 246 * Lower EL using AArch64 : 0x400 - 0x600 247 * --------------------------------------------------------------------- 248 */ 249vector_entry sync_exception_aarch64 250 /* 251 * This exception vector will be the entry point for SMCs and traps 252 * that are unhandled at lower ELs most commonly. SP_EL3 should point 253 * to a valid cpu context where the general purpose and system register 254 * state can be saved. 255 */ 256 check_and_unmask_ea 257 handle_sync_exception 258end_vector_entry sync_exception_aarch64 259 260vector_entry irq_aarch64 261 check_and_unmask_ea 262 handle_interrupt_exception irq_aarch64 263end_vector_entry irq_aarch64 264 265vector_entry fiq_aarch64 266 check_and_unmask_ea 267 handle_interrupt_exception fiq_aarch64 268end_vector_entry fiq_aarch64 269 270vector_entry serror_aarch64 271 msr daifclr, #DAIF_ABT_BIT 272 b enter_lower_el_async_ea 273end_vector_entry serror_aarch64 274 275 /* --------------------------------------------------------------------- 276 * Lower EL using AArch32 : 0x600 - 0x800 277 * --------------------------------------------------------------------- 278 */ 279vector_entry sync_exception_aarch32 280 /* 281 * This exception vector will be the entry point for SMCs and traps 282 * that are unhandled at lower ELs most commonly. SP_EL3 should point 283 * to a valid cpu context where the general purpose and system register 284 * state can be saved. 285 */ 286 check_and_unmask_ea 287 handle_sync_exception 288end_vector_entry sync_exception_aarch32 289 290vector_entry irq_aarch32 291 check_and_unmask_ea 292 handle_interrupt_exception irq_aarch32 293end_vector_entry irq_aarch32 294 295vector_entry fiq_aarch32 296 check_and_unmask_ea 297 handle_interrupt_exception fiq_aarch32 298end_vector_entry fiq_aarch32 299 300vector_entry serror_aarch32 301 msr daifclr, #DAIF_ABT_BIT 302 b enter_lower_el_async_ea 303end_vector_entry serror_aarch32 304 305 306 /* --------------------------------------------------------------------- 307 * This macro takes an argument in x16 that is the index in the 308 * 'rt_svc_descs_indices' array, checks that the value in the array is 309 * valid, and loads in x15 the pointer to the handler of that service. 310 * --------------------------------------------------------------------- 311 */ 312 .macro load_rt_svc_desc_pointer 313 /* Load descriptor index from array of indices */ 314 adr x14, rt_svc_descs_indices 315 ldrb w15, [x14, x16] 316 317#if SMCCC_MAJOR_VERSION == 1 318 /* Any index greater than 127 is invalid. Check bit 7. */ 319 tbnz w15, 7, smc_unknown 320#elif SMCCC_MAJOR_VERSION == 2 321 /* Verify that the top 3 bits of the loaded index are 0 (w15 <= 31) */ 322 cmp w15, #31 323 b.hi smc_unknown 324#endif /* SMCCC_MAJOR_VERSION */ 325 326 /* 327 * Get the descriptor using the index 328 * x11 = (base + off), w15 = index 329 * 330 * handler = (base + off) + (index << log2(size)) 331 */ 332 adr x11, (__RT_SVC_DESCS_START__ + RT_SVC_DESC_HANDLE) 333 lsl w10, w15, #RT_SVC_SIZE_LOG2 334 ldr x15, [x11, w10, uxtw] 335 .endm 336 337 /* --------------------------------------------------------------------- 338 * The following code handles secure monitor calls. 339 * Depending upon the execution state from where the SMC has been 340 * invoked, it frees some general purpose registers to perform the 341 * remaining tasks. They involve finding the runtime service handler 342 * that is the target of the SMC & switching to runtime stacks (SP_EL0) 343 * before calling the handler. 344 * 345 * Note that x30 has been explicitly saved and can be used here 346 * --------------------------------------------------------------------- 347 */ 348func smc_handler 349smc_handler32: 350 /* Check whether aarch32 issued an SMC64 */ 351 tbnz x0, #FUNCID_CC_SHIFT, smc_prohibited 352 353smc_handler64: 354 /* 355 * Populate the parameters for the SMC handler. 356 * We already have x0-x4 in place. x5 will point to a cookie (not used 357 * now). x6 will point to the context structure (SP_EL3) and x7 will 358 * contain flags we need to pass to the handler. 359 * 360 * Save x4-x29 and sp_el0. 361 */ 362 stp x4, x5, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X4] 363 stp x6, x7, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X6] 364 stp x8, x9, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X8] 365 stp x10, x11, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X10] 366 stp x12, x13, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X12] 367 stp x14, x15, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X14] 368 stp x16, x17, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X16] 369 stp x18, x19, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X18] 370 stp x20, x21, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X20] 371 stp x22, x23, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X22] 372 stp x24, x25, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X24] 373 stp x26, x27, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X26] 374 stp x28, x29, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X28] 375 mrs x18, sp_el0 376 str x18, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_SP_EL0] 377 378 mov x5, xzr 379 mov x6, sp 380 381#if SMCCC_MAJOR_VERSION == 1 382 383 /* Get the unique owning entity number */ 384 ubfx x16, x0, #FUNCID_OEN_SHIFT, #FUNCID_OEN_WIDTH 385 ubfx x15, x0, #FUNCID_TYPE_SHIFT, #FUNCID_TYPE_WIDTH 386 orr x16, x16, x15, lsl #FUNCID_OEN_WIDTH 387 388 load_rt_svc_desc_pointer 389 390#elif SMCCC_MAJOR_VERSION == 2 391 392 /* Bit 31 must be set */ 393 tbz x0, #FUNCID_TYPE_SHIFT, smc_unknown 394 395 /* 396 * Check MSB of namespace to decide between compatibility/vendor and 397 * SPCI/SPRT 398 */ 399 tbz x0, #(FUNCID_NAMESPACE_SHIFT + 1), compat_or_vendor 400 401 /* Namespaces SPRT and SPCI currently unimplemented */ 402 b smc_unknown 403 404compat_or_vendor: 405 406 /* Namespace is b'00 (compatibility) or b'01 (vendor) */ 407 408 /* 409 * Add the LSB of the namespace (bit [28]) to the OEN [27:24] to create 410 * a 5-bit index into the rt_svc_descs_indices array. 411 * 412 * The low 16 entries of the rt_svc_descs_indices array correspond to 413 * OENs of the compatibility namespace and the top 16 entries of the 414 * array are assigned to the vendor namespace descriptor. 415 */ 416 ubfx x16, x0, #FUNCID_OEN_SHIFT, #(FUNCID_OEN_WIDTH + 1) 417 418 load_rt_svc_desc_pointer 419 420#endif /* SMCCC_MAJOR_VERSION */ 421 422 /* 423 * Restore the saved C runtime stack value which will become the new 424 * SP_EL0 i.e. EL3 runtime stack. It was saved in the 'cpu_context' 425 * structure prior to the last ERET from EL3. 426 */ 427 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] 428 429 /* Switch to SP_EL0 */ 430 msr spsel, #0 431 432 /* 433 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there is a world 434 * switch during SMC handling. 435 * TODO: Revisit if all system registers can be saved later. 436 */ 437 mrs x16, spsr_el3 438 mrs x17, elr_el3 439 mrs x18, scr_el3 440 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] 441 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] 442 443 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ 444 bfi x7, x18, #0, #1 445 446 mov sp, x12 447 448 /* 449 * Call the Secure Monitor Call handler and then drop directly into 450 * el3_exit() which will program any remaining architectural state 451 * prior to issuing the ERET to the desired lower EL. 452 */ 453#if DEBUG 454 cbz x15, rt_svc_fw_critical_error 455#endif 456 blr x15 457 458 b el3_exit 459 460smc_unknown: 461 /* 462 * Unknown SMC call. Populate return value with SMC_UNK, restore 463 * GP registers, and return to caller. 464 */ 465 mov x0, #SMC_UNK 466 str x0, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] 467 b restore_gp_registers_eret 468 469smc_prohibited: 470 ldr x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] 471 mov x0, #SMC_UNK 472 eret 473 474rt_svc_fw_critical_error: 475 /* Switch to SP_ELx */ 476 msr spsel, #1 477 no_ret report_unhandled_exception 478endfunc smc_handler 479