1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl31.h> 11 #include <bl_common.h> 12 #include <console.h> 13 #include <cortex_a53.h> 14 #include <debug.h> 15 #include <errno.h> 16 #include <generic_delay_timer.h> 17 #include <mmio.h> 18 #include <platform.h> 19 #include <platform_def.h> 20 #include <stddef.h> 21 #include <string.h> 22 #include "hi3798cv200.h" 23 #include "plat_private.h" 24 25 /* Memory ranges for code and RO data sections */ 26 #define BL31_RO_BASE (unsigned long)(&__RO_START__) 27 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) 28 29 /* Memory ranges for coherent memory section */ 30 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 31 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 32 33 #define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45) 34 35 static entry_point_info_t bl32_image_ep_info; 36 static entry_point_info_t bl33_image_ep_info; 37 38 static void hisi_tzpc_sec_init(void) 39 { 40 mmio_write_32(HISI_TZPC_SEC_ATTR_CTRL, TZPC_SEC_ATTR_CTRL_VALUE); 41 } 42 43 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 44 { 45 entry_point_info_t *next_image_info; 46 47 assert(sec_state_is_valid(type)); 48 next_image_info = (type == NON_SECURE) 49 ? &bl33_image_ep_info : &bl32_image_ep_info; 50 /* 51 * None of the images on the ARM development platforms can have 0x0 52 * as the entrypoint 53 */ 54 if (next_image_info->pc) 55 return next_image_info; 56 else 57 return NULL; 58 } 59 60 /******************************************************************************* 61 * Perform any BL31 early platform setup common to ARM standard platforms. 62 * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 63 * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be 64 * done before the MMU is initialized so that the memory layout can be used 65 * while creating page tables. BL2 has flushed this information to memory, so 66 * we are guaranteed to pick up good data. 67 ******************************************************************************/ 68 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 69 u_register_t arg2, u_register_t arg3) 70 { 71 void *from_bl2; 72 73 from_bl2 = (void *) arg0; 74 75 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE); 76 77 /* Init console for crash report */ 78 plat_crash_console_init(); 79 80 /* 81 * Check params passed from BL2 should not be NULL, 82 */ 83 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 84 85 assert(params_from_bl2 != NULL); 86 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 87 assert(params_from_bl2->h.version >= VERSION_2); 88 89 bl_params_node_t *bl_params = params_from_bl2->head; 90 91 /* 92 * Copy BL33 and BL32 (if present), entry point information. 93 * They are stored in Secure RAM, in BL2's address space. 94 */ 95 while (bl_params) { 96 if (bl_params->image_id == BL32_IMAGE_ID) 97 bl32_image_ep_info = *bl_params->ep_info; 98 99 if (bl_params->image_id == BL33_IMAGE_ID) 100 bl33_image_ep_info = *bl_params->ep_info; 101 102 bl_params = bl_params->next_params_info; 103 } 104 105 if (bl33_image_ep_info.pc == 0) 106 panic(); 107 } 108 109 void bl31_platform_setup(void) 110 { 111 /* Init arch timer */ 112 generic_delay_timer_init(); 113 114 /* Init GIC distributor and CPU interface */ 115 poplar_gic_driver_init(); 116 poplar_gic_init(); 117 118 /* Init security properties of IP blocks */ 119 hisi_tzpc_sec_init(); 120 } 121 122 void bl31_plat_runtime_setup(void) 123 { 124 /* do nothing */ 125 } 126 127 void bl31_plat_arch_setup(void) 128 { 129 plat_configure_mmu_el3(BL31_BASE, 130 (BL31_LIMIT - BL31_BASE), 131 BL31_RO_BASE, 132 BL31_RO_LIMIT, 133 BL31_COHERENT_RAM_BASE, 134 BL31_COHERENT_RAM_LIMIT); 135 136 INFO("Boot BL33 from 0x%lx for %lu Bytes\n", 137 bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2); 138 } 139