1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch.h> 8 #include <arch_helpers.h> 9 #include <assert.h> 10 #include <bl_common.h> 11 #include <console.h> 12 #include <context.h> 13 #include <context_mgmt.h> 14 #include <debug.h> 15 #include <platform.h> 16 #include <platform_def.h> 17 #include <platform_sp_min.h> 18 #include <psci.h> 19 #include <runtime_svc.h> 20 #include <smccc_helpers.h> 21 #include <stddef.h> 22 #include <stdint.h> 23 #include <std_svc.h> 24 #include <stdint.h> 25 #include <string.h> 26 #include <utils.h> 27 #include "sp_min_private.h" 28 29 /* Pointers to per-core cpu contexts */ 30 static void *sp_min_cpu_ctx_ptr[PLATFORM_CORE_COUNT]; 31 32 /* SP_MIN only stores the non secure smc context */ 33 static smc_ctx_t sp_min_smc_context[PLATFORM_CORE_COUNT]; 34 35 /****************************************************************************** 36 * Define the smccc helper library API's 37 *****************************************************************************/ 38 void *smc_get_ctx(unsigned int security_state) 39 { 40 assert(security_state == NON_SECURE); 41 return &sp_min_smc_context[plat_my_core_pos()]; 42 } 43 44 void smc_set_next_ctx(unsigned int security_state) 45 { 46 assert(security_state == NON_SECURE); 47 /* SP_MIN stores only non secure smc context. Nothing to do here */ 48 } 49 50 void *smc_get_next_ctx(void) 51 { 52 return &sp_min_smc_context[plat_my_core_pos()]; 53 } 54 55 /******************************************************************************* 56 * This function returns a pointer to the most recent 'cpu_context' structure 57 * for the calling CPU that was set as the context for the specified security 58 * state. NULL is returned if no such structure has been specified. 59 ******************************************************************************/ 60 void *cm_get_context(uint32_t security_state) 61 { 62 assert(security_state == NON_SECURE); 63 return sp_min_cpu_ctx_ptr[plat_my_core_pos()]; 64 } 65 66 /******************************************************************************* 67 * This function sets the pointer to the current 'cpu_context' structure for the 68 * specified security state for the calling CPU 69 ******************************************************************************/ 70 void cm_set_context(void *context, uint32_t security_state) 71 { 72 assert(security_state == NON_SECURE); 73 sp_min_cpu_ctx_ptr[plat_my_core_pos()] = context; 74 } 75 76 /******************************************************************************* 77 * This function returns a pointer to the most recent 'cpu_context' structure 78 * for the CPU identified by `cpu_idx` that was set as the context for the 79 * specified security state. NULL is returned if no such structure has been 80 * specified. 81 ******************************************************************************/ 82 void *cm_get_context_by_index(unsigned int cpu_idx, 83 unsigned int security_state) 84 { 85 assert(security_state == NON_SECURE); 86 return sp_min_cpu_ctx_ptr[cpu_idx]; 87 } 88 89 /******************************************************************************* 90 * This function sets the pointer to the current 'cpu_context' structure for the 91 * specified security state for the CPU identified by CPU index. 92 ******************************************************************************/ 93 void cm_set_context_by_index(unsigned int cpu_idx, void *context, 94 unsigned int security_state) 95 { 96 assert(security_state == NON_SECURE); 97 sp_min_cpu_ctx_ptr[cpu_idx] = context; 98 } 99 100 static void copy_cpu_ctx_to_smc_stx(const regs_t *cpu_reg_ctx, 101 smc_ctx_t *next_smc_ctx) 102 { 103 next_smc_ctx->r0 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R0); 104 next_smc_ctx->r1 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R1); 105 next_smc_ctx->r2 = read_ctx_reg(cpu_reg_ctx, CTX_GPREG_R2); 106 next_smc_ctx->lr_mon = read_ctx_reg(cpu_reg_ctx, CTX_LR); 107 next_smc_ctx->spsr_mon = read_ctx_reg(cpu_reg_ctx, CTX_SPSR); 108 next_smc_ctx->scr = read_ctx_reg(cpu_reg_ctx, CTX_SCR); 109 } 110 111 /******************************************************************************* 112 * This function invokes the PSCI library interface to initialize the 113 * non secure cpu context and copies the relevant cpu context register values 114 * to smc context. These registers will get programmed during `smc_exit`. 115 ******************************************************************************/ 116 static void sp_min_prepare_next_image_entry(void) 117 { 118 entry_point_info_t *next_image_info; 119 cpu_context_t *ctx = cm_get_context(NON_SECURE); 120 u_register_t ns_sctlr; 121 122 /* Program system registers to proceed to non-secure */ 123 next_image_info = sp_min_plat_get_bl33_ep_info(); 124 assert(next_image_info); 125 assert(NON_SECURE == GET_SECURITY_STATE(next_image_info->h.attr)); 126 127 INFO("SP_MIN: Preparing exit to normal world\n"); 128 129 psci_prepare_next_non_secure_ctx(next_image_info); 130 smc_set_next_ctx(NON_SECURE); 131 132 /* Copy r0, lr and spsr from cpu context to SMC context */ 133 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), 134 smc_get_next_ctx()); 135 136 /* Temporarily set the NS bit to access NS SCTLR */ 137 write_scr(read_scr() | SCR_NS_BIT); 138 isb(); 139 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); 140 write_sctlr(ns_sctlr); 141 isb(); 142 143 write_scr(read_scr() & ~SCR_NS_BIT); 144 isb(); 145 } 146 147 /****************************************************************************** 148 * Implement the ARM Standard Service function to get arguments for a 149 * particular service. 150 *****************************************************************************/ 151 uintptr_t get_arm_std_svc_args(unsigned int svc_mask) 152 { 153 /* Setup the arguments for PSCI Library */ 154 DEFINE_STATIC_PSCI_LIB_ARGS_V1(psci_args, sp_min_warm_entrypoint); 155 156 /* PSCI is the only ARM Standard Service implemented */ 157 assert(svc_mask == PSCI_FID_MASK); 158 159 return (uintptr_t)&psci_args; 160 } 161 162 /****************************************************************************** 163 * The SP_MIN main function. Do the platform and PSCI Library setup. Also 164 * initialize the runtime service framework. 165 *****************************************************************************/ 166 void sp_min_main(void) 167 { 168 NOTICE("SP_MIN: %s\n", version_string); 169 NOTICE("SP_MIN: %s\n", build_message); 170 171 /* Perform the SP_MIN platform setup */ 172 sp_min_platform_setup(); 173 174 /* Initialize the runtime services e.g. psci */ 175 INFO("SP_MIN: Initializing runtime services\n"); 176 runtime_svc_init(); 177 178 /* 179 * We are ready to enter the next EL. Prepare entry into the image 180 * corresponding to the desired security state after the next ERET. 181 */ 182 sp_min_prepare_next_image_entry(); 183 184 /* 185 * Perform any platform specific runtime setup prior to cold boot exit 186 * from SP_MIN. 187 */ 188 sp_min_plat_runtime_setup(); 189 190 console_flush(); 191 } 192 193 /****************************************************************************** 194 * This function is invoked during warm boot. Invoke the PSCI library 195 * warm boot entry point which takes care of Architectural and platform setup/ 196 * restore. Copy the relevant cpu_context register values to smc context which 197 * will get programmed during `smc_exit`. 198 *****************************************************************************/ 199 void sp_min_warm_boot(void) 200 { 201 smc_ctx_t *next_smc_ctx; 202 cpu_context_t *ctx = cm_get_context(NON_SECURE); 203 u_register_t ns_sctlr; 204 205 psci_warmboot_entrypoint(); 206 207 smc_set_next_ctx(NON_SECURE); 208 209 next_smc_ctx = smc_get_next_ctx(); 210 zeromem(next_smc_ctx, sizeof(smc_ctx_t)); 211 212 copy_cpu_ctx_to_smc_stx(get_regs_ctx(cm_get_context(NON_SECURE)), 213 next_smc_ctx); 214 215 /* Temporarily set the NS bit to access NS SCTLR */ 216 write_scr(read_scr() | SCR_NS_BIT); 217 isb(); 218 ns_sctlr = read_ctx_reg(get_regs_ctx(ctx), CTX_NS_SCTLR); 219 write_sctlr(ns_sctlr); 220 isb(); 221 222 write_scr(read_scr() & ~SCR_NS_BIT); 223 isb(); 224 } 225 226 #if SP_MIN_WITH_SECURE_FIQ 227 /****************************************************************************** 228 * This function is invoked on secure interrupts. By construction of the 229 * SP_MIN, secure interrupts can only be handled when core executes in non 230 * secure state. 231 *****************************************************************************/ 232 void sp_min_fiq(void) 233 { 234 uint32_t id; 235 236 id = plat_ic_acknowledge_interrupt(); 237 sp_min_plat_fiq_handler(id); 238 plat_ic_end_of_interrupt(id); 239 } 240 #endif /* SP_MIN_WITH_SECURE_FIQ */ 241