1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOC_H__ 8 #define __SOC_H__ 9 10 #include <utils.h> 11 12 #define GLB_SRST_FST_CFG_VAL 0xfdb9 13 #define GLB_SRST_SND_CFG_VAL 0xeca8 14 15 #define PMUCRU_PPLL_CON(n) ((n) * 4) 16 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) 17 #define PLL_MODE_MSK 0x03 18 #define PLL_MODE_SHIFT 0x08 19 #define PLL_BYPASS_MSK 0x01 20 #define PLL_BYPASS_SHIFT 0x01 21 #define PLL_PWRDN_MSK 0x01 22 #define PLL_PWRDN_SHIFT 0x0 23 #define PLL_BYPASS BIT(1) 24 #define PLL_PWRDN BIT(0) 25 26 #define NO_PLL_BYPASS (0x00) 27 #define NO_PLL_PWRDN (0x00) 28 29 #define FBDIV(n) ((0xfff << 16) | n) 30 #define POSTDIV2(n) ((0x7 << (12 + 16)) | (n << 12)) 31 #define POSTDIV1(n) ((0x7 << (8 + 16)) | (n << 8)) 32 #define REFDIV(n) ((0x3F << 16) | n) 33 #define PLL_LOCK(n) ((n >> 31) & 0x1) 34 35 #define PLL_SLOW_MODE BITS_WITH_WMASK(SLOW_MODE,\ 36 PLL_MODE_MSK, PLL_MODE_SHIFT) 37 38 #define PLL_NOMAL_MODE BITS_WITH_WMASK(NORMAL_MODE,\ 39 PLL_MODE_MSK, PLL_MODE_SHIFT) 40 41 #define PLL_BYPASS_MODE BIT_WITH_WMSK(PLL_BYPASS_SHIFT) 42 #define PLL_NO_BYPASS_MODE WMSK_BIT(PLL_BYPASS_SHIFT) 43 44 #define PLL_CON_COUNT 0x06 45 #define CRU_CLKSEL_COUNT 108 46 #define CRU_CLKSEL_CON(n) (0x100 + (n) * 4) 47 48 #define PMUCRU_CLKSEL_CONUT 0x06 49 #define PMUCRU_CLKSEL_OFFSET 0x080 50 #define REG_SIZE 0x04 51 #define REG_SOC_WMSK 0xffff0000 52 #define CLK_GATE_MASK 0x01 53 54 #define PMUCRU_GATE_COUNT 0x03 55 #define CRU_GATE_COUNT 0x23 56 #define PMUCRU_GATE_CON(n) (0x100 + (n) * 4) 57 #define CRU_GATE_CON(n) (0x300 + (n) * 4) 58 59 enum plls_id { 60 ALPLL_ID = 0, 61 ABPLL_ID, 62 DPLL_ID, 63 CPLL_ID, 64 GPLL_ID, 65 NPLL_ID, 66 VPLL_ID, 67 PPLL_ID, 68 END_PLL_ID, 69 }; 70 71 #define CLST_L_CPUS_MSK (0xf) 72 #define CLST_B_CPUS_MSK (0x3) 73 74 enum pll_work_mode { 75 SLOW_MODE = 0x00, 76 NORMAL_MODE = 0x01, 77 DEEP_SLOW_MODE = 0x02, 78 }; 79 80 enum glb_sft_reset { 81 PMU_RST_BY_FIRST_SFT, 82 PMU_RST_BY_SECOND_SFT = BIT(2), 83 PMU_RST_NOT_BY_SFT = BIT(3), 84 }; 85 86 struct pll_div { 87 uint32_t mhz; 88 uint32_t refdiv; 89 uint32_t fbdiv; 90 uint32_t postdiv1; 91 uint32_t postdiv2; 92 uint32_t frac; 93 uint32_t freq; 94 }; 95 96 struct deepsleep_data_s { 97 uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT]; 98 uint32_t cru_gate_con[CRU_GATE_COUNT]; 99 uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT]; 100 }; 101 102 /************************************************** 103 * pmugrf reg, offset 104 **************************************************/ 105 #define PMUGRF_OSREG(n) (0x300 + (n) * 4) 106 107 /************************************************** 108 * DCF reg, offset 109 **************************************************/ 110 #define DCF_DCF_CTRL 0x0 111 #define DCF_DCF_ADDR 0x8 112 #define DCF_DCF_ISR 0xc 113 #define DCF_DCF_TOSET 0x14 114 #define DCF_DCF_TOCMD 0x18 115 #define DCF_DCF_CMD_CFG 0x1c 116 117 /* DCF_DCF_ISR */ 118 #define DCF_TIMEOUT (1 << 2) 119 #define DCF_ERR (1 << 1) 120 #define DCF_DONE (1 << 0) 121 122 /* DCF_DCF_CTRL */ 123 #define DCF_VOP_HW_EN (1 << 2) 124 #define DCF_STOP (1 << 1) 125 #define DCF_START (1 << 0) 126 127 #define CYCL_24M_CNT_US(us) (24 * us) 128 #define CYCL_24M_CNT_MS(ms) (ms * CYCL_24M_CNT_US(1000)) 129 #define CYCL_32K_CNT_MS(ms) (ms * 32) 130 131 /************************************************** 132 * cru reg, offset 133 **************************************************/ 134 #define CRU_SOFTRST_CON(n) (0x400 + (n) * 4) 135 136 #define CRU_DMAC0_RST BIT_WITH_WMSK(3) 137 /* reset release*/ 138 #define CRU_DMAC0_RST_RLS WMSK_BIT(3) 139 140 #define CRU_DMAC1_RST BIT_WITH_WMSK(4) 141 /* reset release*/ 142 #define CRU_DMAC1_RST_RLS WMSK_BIT(4) 143 144 #define CRU_GLB_RST_CON 0x0510 145 #define CRU_GLB_SRST_FST 0x0500 146 #define CRU_GLB_SRST_SND 0x0504 147 148 #define CRU_CLKGATE_CON(n) (0x300 + n * 4) 149 #define PCLK_GPIO2_GATE_SHIFT 3 150 #define PCLK_GPIO3_GATE_SHIFT 4 151 #define PCLK_GPIO4_GATE_SHIFT 5 152 153 /************************************************** 154 * pmu cru reg, offset 155 **************************************************/ 156 #define CRU_PMU_RSTHOLD_CON(n) (0x120 + n * 4) 157 /* reset hold*/ 158 #define CRU_PMU_SGRF_RST_HOLD BIT_WITH_WMSK(6) 159 /* reset hold release*/ 160 #define CRU_PMU_SGRF_RST_RLS WMSK_BIT(6) 161 162 #define CRU_PMU_WDTRST_MSK (0x1 << 4) 163 #define CRU_PMU_WDTRST_EN 0x0 164 165 #define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2) 166 #define CRU_PMU_FIRST_SFTRST_EN 0x0 167 168 #define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4) 169 #define PCLK_GPIO0_GATE_SHIFT 3 170 #define PCLK_GPIO1_GATE_SHIFT 4 171 172 #define CPU_BOOT_ADDR_WMASK 0xffff0000 173 #define CPU_BOOT_ADDR_ALIGN 16 174 175 #define GRF_IOMUX_2BIT_MASK 0x3 176 #define GRF_IOMUX_GPIO 0x0 177 178 #define GRF_GPIO4C2_IOMUX_SHIFT 4 179 #define GRF_GPIO4C2_IOMUX_PWM 0x1 180 #define GRF_GPIO4C6_IOMUX_SHIFT 12 181 #define GRF_GPIO4C6_IOMUX_PWM 0x1 182 183 #define PWM_CNT(n) (0x0000 + 0x10 * (n)) 184 #define PWM_PERIOD_HPR(n) (0x0004 + 0x10 * (n)) 185 #define PWM_DUTY_LPR(n) (0x0008 + 0x10 * (n)) 186 #define PWM_CTRL(n) (0x000c + 0x10 * (n)) 187 188 #define PWM_DISABLE (0 << 0) 189 #define PWM_ENABLE (1 << 0) 190 191 /* grf reg offset */ 192 #define GRF_DDRC0_CON0 0xe380 193 #define GRF_DDRC0_CON1 0xe384 194 #define GRF_DDRC1_CON0 0xe388 195 #define GRF_DDRC1_CON1 0xe38c 196 #define GRF_SOC_CON_BASE 0xe200 197 #define GRF_SOC_CON(n) (GRF_SOC_CON_BASE + (n) * 4) 198 199 #define PMUCRU_CLKSEL_CON0 0x0080 200 #define PMUCRU_CLKGATE_CON2 0x0108 201 #define PMUCRU_SOFTRST_CON0 0x0110 202 #define PMUCRU_GATEDIS_CON0 0x0130 203 #define PMUCRU_SOFTRST_CON(n) (PMUCRU_SOFTRST_CON0 + (n) * 4) 204 205 /* 206 * When system reset in running state, we want the cpus to be reboot 207 * from maskrom (system reboot), 208 * the pmusgrf reset-hold bits needs to be released. 209 * When system wake up from system deep suspend, some soc will be reset 210 * when waked up, 211 * we want the bootcpu to be reboot from pmusram, 212 * the pmusgrf reset-hold bits needs to be held. 213 */ 214 static inline void pmu_sgrf_rst_hld_release(void) 215 { 216 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 217 CRU_PMU_SGRF_RST_RLS); 218 } 219 220 static inline void pmu_sgrf_rst_hld(void) 221 { 222 mmio_write_32(PMUCRU_BASE + CRU_PMU_RSTHOLD_CON(1), 223 CRU_PMU_SGRF_RST_HOLD); 224 } 225 226 /* export related and operating SoC APIs */ 227 void __dead2 soc_global_soft_reset(void); 228 void disable_dvfs_plls(void); 229 void disable_nodvfs_plls(void); 230 void enable_dvfs_plls(void); 231 void enable_nodvfs_plls(void); 232 void prepare_abpll_for_ddrctrl(void); 233 void restore_abpll(void); 234 void restore_dpll(void); 235 void clk_gate_con_save(void); 236 void clk_gate_con_disable(void); 237 void clk_gate_con_restore(void); 238 239 #endif /* __SOC_H__ */ 240