1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <debug.h> 8 #include <mmio.h> 9 #include <plat_sip_calls.h> 10 #include <rockchip_sip_svc.h> 11 #include <runtime_svc.h> 12 #include <dfs.h> 13 14 #define RK_SIP_DDR_CFG 0x82000008 15 #define DRAM_INIT 0x00 16 #define DRAM_SET_RATE 0x01 17 #define DRAM_ROUND_RATE 0x02 18 #define DRAM_SET_AT_SR 0x03 19 #define DRAM_GET_BW 0x04 20 #define DRAM_GET_RATE 0x05 21 #define DRAM_CLR_IRQ 0x06 22 #define DRAM_SET_PARAM 0x07 23 #define DRAM_SET_ODT_PD 0x08 24 25 uint32_t ddr_smc_handler(uint64_t arg0, uint64_t arg1, 26 uint64_t id, uint64_t arg2) 27 { 28 switch (id) { 29 case DRAM_SET_RATE: 30 return ddr_set_rate((uint32_t)arg0); 31 case DRAM_ROUND_RATE: 32 return ddr_round_rate((uint32_t)arg0); 33 case DRAM_GET_RATE: 34 return ddr_get_rate(); 35 case DRAM_SET_ODT_PD: 36 dram_set_odt_pd(arg0, arg1, arg2); 37 break; 38 default: 39 break; 40 } 41 42 return 0; 43 } 44 45 uint64_t rockchip_plat_sip_handler(uint32_t smc_fid, 46 uint64_t x1, 47 uint64_t x2, 48 uint64_t x3, 49 uint64_t x4, 50 void *cookie, 51 void *handle, 52 uint64_t flags) 53 { 54 switch (smc_fid) { 55 case RK_SIP_DDR_CFG: 56 SMC_RET1(handle, ddr_smc_handler(x1, x2, x3, x4)); 57 default: 58 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 59 SMC_RET1(handle, SMC_UNK); 60 } 61 } 62