1 /* 2 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <dw_mmc.h> 13 #include <errno.h> 14 #include <hi6220.h> 15 #include <hikey_def.h> 16 #include <hikey_layout.h> 17 #include <mmc.h> 18 #include <mmio.h> 19 #include <platform.h> 20 #include <string.h> 21 #include <tbbr/tbbr_img_desc.h> 22 23 #include "../../bl1/bl1_private.h" 24 #include "hikey_private.h" 25 26 /* Data structure which holds the extents of the trusted RAM for BL1 */ 27 static meminfo_t bl1_tzram_layout; 28 29 enum { 30 BOOT_NORMAL = 0, 31 BOOT_USB_DOWNLOAD, 32 BOOT_UART_DOWNLOAD, 33 }; 34 35 meminfo_t *bl1_plat_sec_mem_layout(void) 36 { 37 return &bl1_tzram_layout; 38 } 39 40 /* 41 * Perform any BL1 specific platform actions. 42 */ 43 void bl1_early_platform_setup(void) 44 { 45 /* Initialize the console to provide early debug support */ 46 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 47 48 /* Allow BL1 to see the whole Trusted RAM */ 49 bl1_tzram_layout.total_base = BL1_RW_BASE; 50 bl1_tzram_layout.total_size = BL1_RW_SIZE; 51 52 INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT, 53 BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */ 54 } 55 56 /* 57 * Perform the very early platform specific architecture setup here. At the 58 * moment this only does basic initialization. Later architectural setup 59 * (bl1_arch_setup()) does not do anything platform specific. 60 */ 61 void bl1_plat_arch_setup(void) 62 { 63 hikey_init_mmu_el3(bl1_tzram_layout.total_base, 64 bl1_tzram_layout.total_size, 65 BL1_RO_BASE, 66 BL1_RO_LIMIT, 67 BL_COHERENT_RAM_BASE, 68 BL_COHERENT_RAM_END); 69 } 70 71 /* 72 * Function which will perform any remaining platform-specific setup that can 73 * occur after the MMU and data cache have been enabled. 74 */ 75 void bl1_platform_setup(void) 76 { 77 dw_mmc_params_t params; 78 struct mmc_device_info info; 79 80 assert((HIKEY_BL1_MMC_DESC_BASE >= SRAM_BASE) && 81 ((SRAM_BASE + SRAM_SIZE) >= 82 (HIKEY_BL1_MMC_DATA_BASE + HIKEY_BL1_MMC_DATA_SIZE))); 83 hikey_sp804_init(); 84 hikey_gpio_init(); 85 hikey_pmussi_init(); 86 hikey_hi6553_init(); 87 88 hikey_rtc_init(); 89 90 hikey_mmc_pll_init(); 91 92 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 93 params.reg_base = DWMMC0_BASE; 94 params.desc_base = HIKEY_BL1_MMC_DESC_BASE; 95 params.desc_size = 1 << 20; 96 params.clk_rate = 24 * 1000 * 1000; 97 params.bus_width = MMC_BUS_WIDTH_8; 98 params.flags = MMC_FLAG_CMD23; 99 info.mmc_dev_type = MMC_IS_EMMC; 100 dw_mmc_init(¶ms, &info); 101 102 hikey_io_setup(); 103 } 104 105 /* 106 * The following function checks if Firmware update is needed, 107 * by checking if TOC in FIP image is valid or not. 108 */ 109 unsigned int bl1_plat_get_next_image_id(void) 110 { 111 int32_t boot_mode; 112 unsigned int ret; 113 114 boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE); 115 switch (boot_mode) { 116 case BOOT_USB_DOWNLOAD: 117 case BOOT_UART_DOWNLOAD: 118 ret = NS_BL1U_IMAGE_ID; 119 break; 120 default: 121 WARN("Invalid boot mode is found:%d\n", boot_mode); 122 panic(); 123 } 124 return ret; 125 } 126 127 image_desc_t *bl1_plat_get_image_desc(unsigned int image_id) 128 { 129 unsigned int index = 0; 130 131 while (bl1_tbbr_image_descs[index].image_id != INVALID_IMAGE_ID) { 132 if (bl1_tbbr_image_descs[index].image_id == image_id) 133 return &bl1_tbbr_image_descs[index]; 134 135 index++; 136 } 137 138 return NULL; 139 } 140 141 void bl1_plat_set_ep_info(unsigned int image_id, 142 entry_point_info_t *ep_info) 143 { 144 uint64_t data = 0; 145 146 if (image_id == BL2_IMAGE_ID) 147 panic(); 148 inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE); 149 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 150 do { 151 data |= 3 << 20; 152 __asm__ volatile ("msr cpacr_el1, %0" : : "r"(data)); 153 __asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data)); 154 } while ((data & (3 << 20)) != (3 << 20)); 155 INFO("cpacr_el1:0x%llx\n", data); 156 157 ep_info->args.arg0 = 0xffff & read_mpidr(); 158 ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, 159 DISABLE_ALL_EXCEPTIONS); 160 } 161