1 /* 2 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLAT_PRIVATE_H__ 8 #define __PLAT_PRIVATE_H__ 9 10 #ifndef __ASSEMBLY__ 11 #include <mmio.h> 12 #include <stdint.h> 13 #include <xlat_tables.h> 14 #include <psci.h> 15 16 #define __sramdata __attribute__((section(".sram.data"))) 17 #define __sramconst __attribute__((section(".sram.rodata"))) 18 #define __sramfunc __attribute__((section(".sram.text"))) \ 19 __attribute__((noinline)) 20 21 extern uint32_t __bl31_sram_text_start, __bl31_sram_text_end; 22 extern uint32_t __bl31_sram_data_start, __bl31_sram_data_end; 23 extern uint32_t __sram_incbin_start, __sram_incbin_end; 24 25 26 /****************************************************************************** 27 * The register have write-mask bits, it is mean, if you want to set the bits, 28 * you needs set the write-mask bits at the same time, 29 * The write-mask bits is in high 16-bits. 30 * The fllowing macro definition helps access write-mask bits reg efficient! 31 ******************************************************************************/ 32 #define REG_MSK_SHIFT 16 33 34 #ifndef WMSK_BIT 35 #define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT) 36 #endif 37 38 /* set one bit with write mask */ 39 #ifndef BIT_WITH_WMSK 40 #define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr)) 41 #endif 42 43 #ifndef BITS_SHIFT 44 #define BITS_SHIFT(bits, shift) (bits << (shift)) 45 #endif 46 47 #ifndef BITS_WITH_WMASK 48 #define BITS_WITH_WMASK(bits, msk, shift)\ 49 (BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, (shift + REG_MSK_SHIFT))) 50 #endif 51 52 /****************************************************************************** 53 * Function and variable prototypes 54 *****************************************************************************/ 55 void plat_configure_mmu_el3(unsigned long total_base, 56 unsigned long total_size, 57 unsigned long, 58 unsigned long, 59 unsigned long, 60 unsigned long); 61 62 void plat_cci_init(void); 63 void plat_cci_enable(void); 64 void plat_cci_disable(void); 65 66 void plat_delay_timer_init(void); 67 68 void params_early_setup(void *plat_params_from_bl2); 69 70 void plat_rockchip_gic_driver_init(void); 71 void plat_rockchip_gic_init(void); 72 void plat_rockchip_gic_cpuif_enable(void); 73 void plat_rockchip_gic_cpuif_disable(void); 74 void plat_rockchip_gic_pcpu_init(void); 75 76 void plat_rockchip_pmusram_prepare(void); 77 void plat_rockchip_pmu_init(void); 78 void plat_rockchip_soc_init(void); 79 uintptr_t plat_get_sec_entrypoint(void); 80 81 void platform_cpu_warmboot(void); 82 83 struct gpio_info *plat_get_rockchip_gpio_reset(void); 84 struct gpio_info *plat_get_rockchip_gpio_poweroff(void); 85 struct gpio_info *plat_get_rockchip_suspend_gpio(uint32_t *count); 86 struct apio_info *plat_get_rockchip_suspend_apio(void); 87 void plat_rockchip_gpio_init(void); 88 89 int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint); 90 int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl, 91 plat_local_state_t lvl_state); 92 int rockchip_soc_cores_pwr_dm_off(void); 93 int rockchip_soc_sys_pwr_dm_suspend(void); 94 int rockchip_soc_cores_pwr_dm_suspend(void); 95 int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, 96 plat_local_state_t lvl_state); 97 int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl, 98 plat_local_state_t lvl_state); 99 int rockchip_soc_cores_pwr_dm_on_finish(void); 100 int rockchip_soc_sys_pwr_dm_resume(void); 101 102 int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, 103 plat_local_state_t lvl_state); 104 int rockchip_soc_cores_pwr_dm_resume(void); 105 void __dead2 rockchip_soc_soft_reset(void); 106 void __dead2 rockchip_soc_system_off(void); 107 void __dead2 rockchip_soc_cores_pd_pwr_dn_wfi( 108 const psci_power_state_t *target_state); 109 void __dead2 rockchip_soc_sys_pd_pwr_dn_wfi(void); 110 111 extern const unsigned char rockchip_power_domain_tree_desc[]; 112 113 extern void *pmu_cpuson_entrypoint_start; 114 extern void *pmu_cpuson_entrypoint_end; 115 extern uint64_t cpuson_entry_point[PLATFORM_CORE_COUNT]; 116 extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT]; 117 118 extern const mmap_region_t plat_rk_mmap[]; 119 120 void rockchip_plat_sram_mmu_el3(void); 121 void plat_rockchip_mem_prepare(void); 122 123 #endif /* __ASSEMBLY__ */ 124 125 /****************************************************************************** 126 * cpu up status 127 * The bits of macro value is not more than 12 bits for cmp instruction! 128 ******************************************************************************/ 129 #define PMU_CPU_HOTPLUG 0xf00 130 #define PMU_CPU_AUTO_PWRDN 0xf0 131 #define PMU_CLST_RET 0xa5 132 133 #endif /* __PLAT_PRIVATE_H__ */ 134