1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <bl_common.h> 9 #include <console.h> 10 #include <debug.h> 11 #include <mmio.h> 12 #include <pl011.h> 13 #include <plat_arm.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <platform_sp_min.h> 17 18 static entry_point_info_t bl33_image_ep_info; 19 20 /* Weak definitions may be overridden in specific ARM standard platform */ 21 #pragma weak sp_min_platform_setup 22 #pragma weak sp_min_plat_arch_setup 23 #pragma weak plat_arm_sp_min_early_platform_setup 24 25 #define MAP_BL_SP_MIN_TOTAL MAP_REGION_FLAT( \ 26 BL32_BASE, \ 27 BL32_END - BL32_BASE, \ 28 MT_MEMORY | MT_RW | MT_SECURE) 29 30 /* 31 * Check that BL32_BASE is above ARM_TB_FW_CONFIG_LIMIT. The reserved page 32 * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2. 33 */ 34 CASSERT(BL32_BASE >= ARM_TB_FW_CONFIG_LIMIT, assert_bl32_base_overflows); 35 36 /******************************************************************************* 37 * Return a pointer to the 'entry_point_info' structure of the next image for the 38 * security state specified. BL33 corresponds to the non-secure image type 39 * while BL32 corresponds to the secure image type. A NULL pointer is returned 40 * if the image does not exist. 41 ******************************************************************************/ 42 entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) 43 { 44 entry_point_info_t *next_image_info; 45 46 next_image_info = &bl33_image_ep_info; 47 48 /* 49 * None of the images on the ARM development platforms can have 0x0 50 * as the entrypoint 51 */ 52 if (next_image_info->pc) 53 return next_image_info; 54 else 55 return NULL; 56 } 57 58 /******************************************************************************* 59 * Utility function to perform early platform setup. 60 ******************************************************************************/ 61 void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, 62 uintptr_t hw_config, void *plat_params_from_bl2) 63 { 64 /* Initialize the console to provide early debug support */ 65 arm_console_boot_init(); 66 67 #if RESET_TO_SP_MIN 68 /* There are no parameters from BL2 if SP_MIN is a reset vector */ 69 assert(from_bl2 == NULL); 70 assert(plat_params_from_bl2 == NULL); 71 72 /* Populate entry point information for BL33 */ 73 SET_PARAM_HEAD(&bl33_image_ep_info, 74 PARAM_EP, 75 VERSION_1, 76 0); 77 /* 78 * Tell SP_MIN where the non-trusted software image 79 * is located and the entry state information 80 */ 81 bl33_image_ep_info.pc = plat_get_ns_image_entrypoint(); 82 bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry(); 83 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 84 85 # if ARM_LINUX_KERNEL_AS_BL33 86 /* 87 * According to the file ``Documentation/arm/Booting`` of the Linux 88 * kernel tree, Linux expects: 89 * r0 = 0 90 * r1 = machine type number, optional in DT-only platforms (~0 if so) 91 * r2 = Physical address of the device tree blob 92 */ 93 bl33_image_ep_info.args.arg0 = 0U; 94 bl33_image_ep_info.args.arg1 = ~0U; 95 bl33_image_ep_info.args.arg2 = (u_register_t)ARM_PRELOADED_DTB_BASE; 96 # endif 97 98 #else /* RESET_TO_SP_MIN */ 99 100 /* 101 * Check params passed from BL2 should not be NULL, 102 */ 103 bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2; 104 assert(params_from_bl2 != NULL); 105 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 106 assert(params_from_bl2->h.version >= VERSION_2); 107 108 bl_params_node_t *bl_params = params_from_bl2->head; 109 110 /* 111 * Copy BL33 entry point information. 112 * They are stored in Secure RAM, in BL2's address space. 113 */ 114 while (bl_params) { 115 if (bl_params->image_id == BL33_IMAGE_ID) { 116 bl33_image_ep_info = *bl_params->ep_info; 117 break; 118 } 119 120 bl_params = bl_params->next_params_info; 121 } 122 123 if (bl33_image_ep_info.pc == 0) 124 panic(); 125 126 #endif /* RESET_TO_SP_MIN */ 127 128 } 129 130 /******************************************************************************* 131 * Default implementation for sp_min_platform_setup2() for ARM platforms 132 ******************************************************************************/ 133 void plat_arm_sp_min_early_platform_setup(u_register_t arg0, u_register_t arg1, 134 u_register_t arg2, u_register_t arg3) 135 { 136 arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); 137 138 /* 139 * Initialize Interconnect for this cluster during cold boot. 140 * No need for locks as no other CPU is active. 141 */ 142 plat_arm_interconnect_init(); 143 144 /* 145 * Enable Interconnect coherency for the primary CPU's cluster. 146 * Earlier bootloader stages might already do this (e.g. Trusted 147 * Firmware's BL1 does it) but we can't assume so. There is no harm in 148 * executing this code twice anyway. 149 * Platform specific PSCI code will enable coherency for other 150 * clusters. 151 */ 152 plat_arm_interconnect_enter_coherency(); 153 } 154 155 void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, 156 u_register_t arg2, u_register_t arg3) 157 { 158 plat_arm_sp_min_early_platform_setup(arg0, arg1, arg2, arg3); 159 } 160 161 /******************************************************************************* 162 * Perform any SP_MIN platform runtime setup prior to SP_MIN exit. 163 * Common to ARM standard platforms. 164 ******************************************************************************/ 165 void arm_sp_min_plat_runtime_setup(void) 166 { 167 /* Initialize the runtime console */ 168 arm_console_runtime_init(); 169 } 170 171 /******************************************************************************* 172 * Perform platform specific setup for SP_MIN 173 ******************************************************************************/ 174 void sp_min_platform_setup(void) 175 { 176 /* Initialize the GIC driver, cpu and distributor interfaces */ 177 plat_arm_gic_driver_init(); 178 plat_arm_gic_init(); 179 180 /* 181 * Do initial security configuration to allow DRAM/device access 182 * (if earlier BL has not already done so). 183 */ 184 #if RESET_TO_SP_MIN 185 plat_arm_security_setup(); 186 187 #if defined(PLAT_ARM_MEM_PROT_ADDR) 188 arm_nor_psci_do_dyn_mem_protect(); 189 #endif /* PLAT_ARM_MEM_PROT_ADDR */ 190 191 #endif 192 193 /* Enable and initialize the System level generic timer */ 194 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 195 CNTCR_FCREQ(0U) | CNTCR_EN); 196 197 /* Allow access to the System counter timer module */ 198 arm_configure_sys_timer(); 199 200 /* Initialize power controller before setting up topology */ 201 plat_arm_pwrc_setup(); 202 } 203 204 void sp_min_plat_runtime_setup(void) 205 { 206 arm_sp_min_plat_runtime_setup(); 207 } 208 209 /******************************************************************************* 210 * Perform the very early platform specific architectural setup here. At the 211 * moment this only initializes the MMU 212 ******************************************************************************/ 213 void sp_min_plat_arch_setup(void) 214 { 215 const mmap_region_t bl_regions[] = { 216 MAP_BL_SP_MIN_TOTAL, 217 ARM_MAP_BL_RO, 218 #if USE_COHERENT_MEM 219 ARM_MAP_BL_COHERENT_RAM, 220 #endif 221 {0} 222 }; 223 224 setup_page_tables(bl_regions, plat_arm_get_mmap()); 225 226 enable_mmu_svc_mon(0); 227 } 228