1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <debug.h> 9 #include <mmio.h> 10 #include <platform_def.h> 11 #include <plat_private.h> 12 #include <rk3368_def.h> 13 #include <soc.h> 14 15 static uint32_t plls_con[END_PLL_ID][4]; 16 17 /* Table of regions to map using the MMU. */ 18 const mmap_region_t plat_rk_mmap[] = { 19 MAP_REGION_FLAT(CCI400_BASE, CCI400_SIZE, 20 MT_DEVICE | MT_RW | MT_SECURE), 21 MAP_REGION_FLAT(GIC400_BASE, GIC400_SIZE, 22 MT_DEVICE | MT_RW | MT_SECURE), 23 MAP_REGION_FLAT(STIME_BASE, STIME_SIZE, 24 MT_DEVICE | MT_RW | MT_SECURE), 25 MAP_REGION_FLAT(SGRF_BASE, SGRF_SIZE, 26 MT_DEVICE | MT_RW | MT_SECURE), 27 MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE, 28 MT_MEMORY | MT_RW | MT_SECURE), 29 MAP_REGION_FLAT(PMU_BASE, PMU_SIZE, 30 MT_DEVICE | MT_RW | MT_SECURE), 31 MAP_REGION_FLAT(UART_DBG_BASE, UART_DBG_SIZE, 32 MT_DEVICE | MT_RW | MT_SECURE), 33 MAP_REGION_FLAT(CRU_BASE, CRU_SIZE, 34 MT_DEVICE | MT_RW | MT_SECURE), 35 MAP_REGION_FLAT(DDR_PCTL_BASE, DDR_PCTL_SIZE, 36 MT_DEVICE | MT_RW | MT_SECURE), 37 MAP_REGION_FLAT(DDR_PHY_BASE, DDR_PHY_SIZE, 38 MT_DEVICE | MT_RW | MT_SECURE), 39 MAP_REGION_FLAT(GRF_BASE, GRF_SIZE, 40 MT_DEVICE | MT_RW | MT_SECURE), 41 MAP_REGION_FLAT(SERVICE_BUS_BASE, SERVICE_BUS_SISE, 42 MT_DEVICE | MT_RW | MT_SECURE), 43 { 0 } 44 }; 45 46 /* The RockChip power domain tree descriptor */ 47 const unsigned char rockchip_power_domain_tree_desc[] = { 48 /* No of root nodes */ 49 PLATFORM_SYSTEM_COUNT, 50 /* No of children for the root node */ 51 PLATFORM_CLUSTER_COUNT, 52 /* No of children for the first cluster node */ 53 PLATFORM_CLUSTER0_CORE_COUNT, 54 /* No of children for the second cluster node */ 55 PLATFORM_CLUSTER1_CORE_COUNT 56 }; 57 58 void secure_timer_init(void) 59 { 60 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT0, 0xffffffff); 61 mmio_write_32(STIMER1_BASE + TIMER_LOADE_COUNT1, 0xffffffff); 62 63 /* auto reload & enable the timer */ 64 mmio_write_32(STIMER1_BASE + TIMER_CONTROL_REG, TIMER_EN); 65 } 66 67 void sgrf_init(void) 68 { 69 /* setting all configurable ip into no-secure */ 70 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(5), SGRF_SOC_CON_NS); 71 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(6), SGRF_SOC_CON7_BITS); 72 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(7), SGRF_SOC_CON_NS); 73 74 /* secure dma to no sesure */ 75 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(0), SGRF_BUSDMAC_CON0_NS); 76 mmio_write_32(SGRF_BASE + SGRF_BUSDMAC_CON(1), SGRF_BUSDMAC_CON1_NS); 77 dsb(); 78 79 /* rst dma1 */ 80 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), 81 RST_DMA1_MSK | (RST_DMA1_MSK << 16)); 82 /* rst dma2 */ 83 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), 84 RST_DMA2_MSK | (RST_DMA2_MSK << 16)); 85 86 dsb(); 87 88 /* release dma1 rst*/ 89 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(1), (RST_DMA1_MSK << 16)); 90 /* release dma2 rst*/ 91 mmio_write_32(CRU_BASE + CRU_SOFTRSTS_CON(4), (RST_DMA2_MSK << 16)); 92 } 93 94 void plat_rockchip_soc_init(void) 95 { 96 secure_timer_init(); 97 sgrf_init(); 98 } 99 100 void regs_updata_bits(uintptr_t addr, uint32_t val, 101 uint32_t mask, uint32_t shift) 102 { 103 uint32_t tmp, orig; 104 105 orig = mmio_read_32(addr); 106 107 tmp = orig & ~(mask << shift); 108 tmp |= (val & mask) << shift; 109 110 if (tmp != orig) 111 mmio_write_32(addr, tmp); 112 dsb(); 113 } 114 115 static void plls_suspend(uint32_t pll_id) 116 { 117 plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); 118 plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); 119 plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); 120 plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); 121 122 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); 123 mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); 124 } 125 126 static void pm_plls_suspend(void) 127 { 128 plls_suspend(NPLL_ID); 129 plls_suspend(CPLL_ID); 130 plls_suspend(GPLL_ID); 131 plls_suspend(ABPLL_ID); 132 plls_suspend(ALPLL_ID); 133 } 134 135 static inline void plls_resume(void) 136 { 137 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 138 plls_con[ABPLL_ID][3] | PLL_BYPASS_W_MSK); 139 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 140 plls_con[ALPLL_ID][3] | PLL_BYPASS_W_MSK); 141 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 142 plls_con[GPLL_ID][3] | PLL_BYPASS_W_MSK); 143 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 144 plls_con[CPLL_ID][3] | PLL_BYPASS_W_MSK); 145 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 146 plls_con[NPLL_ID][3] | PLL_BYPASS_W_MSK); 147 } 148 149 void soc_sleep_config(void) 150 { 151 int i = 0; 152 153 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 154 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 155 pm_plls_suspend(); 156 157 for (i = 0; i < CRU_CLKGATES_CON_CNT; i++) 158 mmio_write_32(CRU_BASE + CRU_CLKGATES_CON(i), 0xffff0000); 159 } 160 161 void pm_plls_resume(void) 162 { 163 plls_resume(); 164 165 mmio_write_32(CRU_BASE + PLL_CONS(ABPLL_ID, 3), 166 plls_con[ABPLL_ID][3] | PLLS_MODE_WMASK); 167 mmio_write_32(CRU_BASE + PLL_CONS(ALPLL_ID, 3), 168 plls_con[ALPLL_ID][3] | PLLS_MODE_WMASK); 169 mmio_write_32(CRU_BASE + PLL_CONS(GPLL_ID, 3), 170 plls_con[GPLL_ID][3] | PLLS_MODE_WMASK); 171 mmio_write_32(CRU_BASE + PLL_CONS(CPLL_ID, 3), 172 plls_con[CPLL_ID][3] | PLLS_MODE_WMASK); 173 mmio_write_32(CRU_BASE + PLL_CONS(NPLL_ID, 3), 174 plls_con[NPLL_ID][3] | PLLS_MODE_WMASK); 175 } 176 177 void __dead2 rockchip_soc_soft_reset(void) 178 { 179 uint32_t temp_val; 180 181 mmio_write_32(CRU_BASE + PLL_CONS((GPLL_ID), 3), PLL_SLOW_BITS); 182 mmio_write_32(CRU_BASE + PLL_CONS((CPLL_ID), 3), PLL_SLOW_BITS); 183 mmio_write_32(CRU_BASE + PLL_CONS((NPLL_ID), 3), PLL_SLOW_BITS); 184 mmio_write_32(CRU_BASE + PLL_CONS((ABPLL_ID), 3), PLL_SLOW_BITS); 185 mmio_write_32(CRU_BASE + PLL_CONS((ALPLL_ID), 3), PLL_SLOW_BITS); 186 187 temp_val = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON) | 188 PMU_RST_BY_SECOND_SFT; 189 190 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, temp_val); 191 mmio_write_32(CRU_BASE + CRU_GLB_SRST_SND, 0xeca8); 192 193 /* 194 * Maybe the HW needs some times to reset the system, 195 * so we do not hope the core to excute valid codes. 196 */ 197 while (1) 198 ; 199 } 200