1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __MCE_PRIVATE_H__ 8 #define __MCE_PRIVATE_H__ 9 10 #include <mmio.h> 11 #include <tegra_def.h> 12 13 /******************************************************************************* 14 * Macros to prepare CSTATE info request 15 ******************************************************************************/ 16 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 17 #define CLUSTER_CSTATE_MASK 0x7ULL 18 #define CLUSTER_CSTATE_SHIFT 0U 19 #define CLUSTER_CSTATE_UPDATE_BIT (1ULL << 7) 20 #define CCPLEX_CSTATE_MASK 0x3ULL 21 #define CCPLEX_CSTATE_SHIFT 8ULL 22 #define CCPLEX_CSTATE_UPDATE_BIT (1ULL << 15) 23 #define SYSTEM_CSTATE_MASK 0xFULL 24 #define SYSTEM_CSTATE_SHIFT 16ULL 25 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22ULL 26 #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1ULL << 22) 27 #define SYSTEM_CSTATE_UPDATE_BIT (1ULL << 23) 28 #define CSTATE_WAKE_MASK_UPDATE_BIT (1ULL << 31) 29 #define CSTATE_WAKE_MASK_SHIFT 32ULL 30 #define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU 31 32 /******************************************************************************* 33 * Auto-CC3 control macros 34 ******************************************************************************/ 35 #define MCE_AUTO_CC3_FREQ_MASK 0x1FFU 36 #define MCE_AUTO_CC3_FREQ_SHIFT 0U 37 #define MCE_AUTO_CC3_VTG_MASK 0x7FU 38 #define MCE_AUTO_CC3_VTG_SHIFT 16U 39 #define MCE_AUTO_CC3_ENABLE_BIT (1U << 31) 40 41 /******************************************************************************* 42 * Macros for the 'IS_SC7_ALLOWED' command 43 ******************************************************************************/ 44 #define MCE_SC7_ALLOWED_MASK 0x7U 45 #define MCE_SC7_WAKE_TIME_SHIFT 32U 46 47 /******************************************************************************* 48 * Macros for 'read/write ctats' commands 49 ******************************************************************************/ 50 #define MCE_CSTATE_STATS_TYPE_SHIFT 32ULL 51 #define MCE_CSTATE_WRITE_DATA_LO_MASK 0xFU 52 53 /******************************************************************************* 54 * Macros for 'update crossover threshold' command 55 ******************************************************************************/ 56 #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32U 57 58 /******************************************************************************* 59 * MCA command struct 60 ******************************************************************************/ 61 typedef union mca_cmd { 62 struct command { 63 uint8_t cmd; 64 uint8_t idx; 65 uint8_t subidx; 66 } command; 67 struct input { 68 uint32_t low; 69 uint32_t high; 70 } input; 71 uint64_t data; 72 } mca_cmd_t; 73 74 /******************************************************************************* 75 * MCA argument struct 76 ******************************************************************************/ 77 typedef union mca_arg { 78 struct err { 79 uint32_t error:8; 80 uint32_t unused:24; 81 uint32_t unused2:24; 82 uint32_t finish:8; 83 } err; 84 struct arg { 85 uint32_t low; 86 uint32_t high; 87 } arg; 88 uint64_t data; 89 } mca_arg_t; 90 91 /******************************************************************************* 92 * Uncore PERFMON ARI struct 93 ******************************************************************************/ 94 typedef union uncore_perfmon_req { 95 struct perfmon_command { 96 /* 97 * Commands: 0 = READ, 1 = WRITE 98 */ 99 uint32_t cmd:8; 100 /* 101 * The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4 102 */ 103 uint32_t grp:4; 104 /* 105 * Unit selector: Selects the unit instance, with 0 = Unit 106 * = (number of units in group) - 1. 107 */ 108 uint32_t unit:4; 109 /* 110 * Selects the uncore perfmon register to access 111 */ 112 uint32_t reg:8; 113 /* 114 * Counter number. Selects which counter to use for 115 * registers NV_PMEVCNTR and NV_PMEVTYPER. 116 */ 117 uint32_t counter:8; 118 } perfmon_command; 119 struct perfmon_status { 120 /* 121 * Resulting command status 122 */ 123 uint32_t val:8; 124 uint32_t unused:24; 125 } perfmon_status; 126 uint64_t data; 127 } uncore_perfmon_req_t; 128 129 #define UNCORE_PERFMON_CMD_READ 0U 130 #define UNCORE_PERFMON_CMD_WRITE 1U 131 132 #define UNCORE_PERFMON_CMD_MASK 0xFFU 133 #define UNCORE_PERFMON_UNIT_GRP_MASK 0xFU 134 #define UNCORE_PERFMON_SELECTOR_MASK 0xFU 135 #define UNCORE_PERFMON_REG_MASK 0xFFU 136 #define UNCORE_PERFMON_CTR_MASK 0xFFU 137 #define UNCORE_PERFMON_RESP_STATUS_MASK 0xFFU 138 139 /******************************************************************************* 140 * Structure populated by arch specific code to export routines which perform 141 * common low level MCE functions 142 ******************************************************************************/ 143 typedef struct arch_mce_ops { 144 /* 145 * This ARI request sets up the MCE to start execution on assertion 146 * of STANDBYWFI, update the core power state and expected wake time, 147 * then determine the proper power state to enter. 148 */ 149 int (*enter_cstate)(uint32_t ari_base, uint32_t state, 150 uint32_t wake_time); 151 /* 152 * This ARI request allows updating of the CLUSTER_CSTATE, 153 * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. 154 */ 155 int (*update_cstate_info)(uint32_t ari_base, 156 uint32_t cluster, 157 uint32_t ccplex, 158 uint32_t system, 159 uint8_t sys_state_force, 160 uint32_t wake_mask, 161 uint8_t update_wake_mask); 162 /* 163 * This ARI request allows updating of power state crossover 164 * threshold times. An index value specifies which crossover 165 * state is being updated. 166 */ 167 int (*update_crossover_time)(uint32_t ari_base, 168 uint32_t type, 169 uint32_t time); 170 /* 171 * This ARI request allows read access to statistical information 172 * related to power states. 173 */ 174 uint64_t (*read_cstate_stats)(uint32_t ari_base, 175 uint32_t state); 176 /* 177 * This ARI request allows write access to statistical information 178 * related to power states. 179 */ 180 int (*write_cstate_stats)(uint32_t ari_base, 181 uint32_t state, 182 uint32_t stats); 183 /* 184 * This ARI request allows the CPU to understand the features 185 * supported by the MCE firmware. 186 */ 187 uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, 188 uint32_t data); 189 /* 190 * This ARI request allows querying the CCPLEX to determine if 191 * the CCx state is allowed given a target core C-state and wake 192 * time. If the CCx state is allowed, the response indicates CCx 193 * must be entered. If the CCx state is not allowed, the response 194 * indicates CC6/CC7 can't be entered 195 */ 196 int (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, 197 uint32_t wake_time); 198 /* 199 * This ARI request allows querying the CCPLEX to determine if 200 * the SC7 state is allowed given a target core C-state and wake 201 * time. If the SC7 state is allowed, all cores but the associated 202 * core are offlined (WAKE_EVENTS are set to 0) and the response 203 * indicates SC7 must be entered. If the SC7 state is not allowed, 204 * the response indicates SC7 can't be entered 205 */ 206 int (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, 207 uint32_t wake_time); 208 /* 209 * This ARI request allows a core to bring another offlined core 210 * back online to the C0 state. Note that a core is offlined by 211 * entering a C-state where the WAKE_MASK is all 0. 212 */ 213 int (*online_core)(uint32_t ari_base, uint32_t cpuid); 214 /* 215 * This ARI request allows the CPU to enable/disable Auto-CC3 idle 216 * state. 217 */ 218 int (*cc3_ctrl)(uint32_t ari_base, 219 uint32_t freq, 220 uint32_t volt, 221 uint8_t enable); 222 /* 223 * This ARI request allows updating the reset vector register for 224 * D15 and A57 CPUs. 225 */ 226 int (*update_reset_vector)(uint32_t ari_base); 227 /* 228 * This ARI request instructs the ROC to flush A57 data caches in 229 * order to maintain coherency with the Denver cluster. 230 */ 231 int (*roc_flush_cache)(uint32_t ari_base); 232 /* 233 * This ARI request instructs the ROC to flush A57 data caches along 234 * with the caches covering ARM code in order to maintain coherency 235 * with the Denver cluster. 236 */ 237 int (*roc_flush_cache_trbits)(uint32_t ari_base); 238 /* 239 * This ARI request instructs the ROC to clean A57 data caches along 240 * with the caches covering ARM code in order to maintain coherency 241 * with the Denver cluster. 242 */ 243 int (*roc_clean_cache)(uint32_t ari_base); 244 /* 245 * This ARI request reads/writes the Machine Check Arch. (MCA) 246 * registers. 247 */ 248 uint64_t (*read_write_mca)(uint32_t ari_base, 249 mca_cmd_t cmd, 250 uint64_t *data); 251 /* 252 * Some MC GSC (General Security Carveout) register values are 253 * expected to be changed by TrustZone secure ARM code after boot. 254 * Since there is no hardware mechanism for the CCPLEX to know 255 * that an MC GSC register has changed to allow it to update its 256 * own internal GSC register, there needs to be a mechanism that 257 * can be used by ARM code to cause the CCPLEX to update its GSC 258 * register value. This ARI request allows updating the GSC register 259 * value for a certain carveout in the CCPLEX. 260 */ 261 int (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); 262 /* 263 * This ARI request instructs the CCPLEX to either shutdown or 264 * reset the entire system 265 */ 266 void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); 267 /* 268 * This ARI request reads/writes data from/to Uncore PERFMON 269 * registers 270 */ 271 int (*read_write_uncore_perfmon)(uint32_t ari_base, 272 uncore_perfmon_req_t req, uint64_t *data); 273 /* 274 * This ARI implements ARI_MISC_CCPLEX commands. This can be 275 * used to enable/disable coresight clock gating. 276 */ 277 void (*misc_ccplex)(uint32_t ari_base, uint32_t index, 278 uint32_t value); 279 } arch_mce_ops_t; 280 281 /* declarations for ARI/NVG handler functions */ 282 int ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 283 int ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 284 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 285 uint8_t update_wake_mask); 286 int ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 287 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); 288 int ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 289 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); 290 int ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 291 int ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 292 int ari_online_core(uint32_t ari_base, uint32_t core); 293 int ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 294 int ari_reset_vector_update(uint32_t ari_base); 295 int ari_roc_flush_cache_trbits(uint32_t ari_base); 296 int ari_roc_flush_cache(uint32_t ari_base); 297 int ari_roc_clean_cache(uint32_t ari_base); 298 uint64_t ari_read_write_mca(uint32_t ari_base, mca_cmd_t cmd, uint64_t *data); 299 int ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); 300 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); 301 int ari_read_write_uncore_perfmon(uint32_t ari_base, 302 uncore_perfmon_req_t req, uint64_t *data); 303 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); 304 305 int nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 306 int nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 307 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 308 uint8_t update_wake_mask); 309 int nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 310 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); 311 int nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t val); 312 int nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 313 int nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 314 int nvg_online_core(uint32_t ari_base, uint32_t core); 315 int nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 316 317 #endif /* __MCE_PRIVATE_H__ */ 318