1 /* 2 * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MCE_PRIVATE_H 8 #define MCE_PRIVATE_H 9 10 #include <mmio.h> 11 #include <tegra_def.h> 12 13 /******************************************************************************* 14 * Macros to prepare CSTATE info request 15 ******************************************************************************/ 16 /* Description of the parameters for UPDATE_CSTATE_INFO request */ 17 #define CLUSTER_CSTATE_MASK ULL(0x7) 18 #define CLUSTER_CSTATE_SHIFT U(0) 19 #define CLUSTER_CSTATE_UPDATE_BIT (ULL(1) << 7) 20 #define CCPLEX_CSTATE_MASK ULL(0x3) 21 #define CCPLEX_CSTATE_SHIFT ULL(8) 22 #define CCPLEX_CSTATE_UPDATE_BIT (ULL(1) << 15) 23 #define SYSTEM_CSTATE_MASK ULL(0xF) 24 #define SYSTEM_CSTATE_SHIFT ULL(16) 25 #define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT ULL(22) 26 #define SYSTEM_CSTATE_FORCE_UPDATE_BIT (ULL(1) << 22) 27 #define SYSTEM_CSTATE_UPDATE_BIT (ULL(1) << 23) 28 #define CSTATE_WAKE_MASK_UPDATE_BIT (ULL(1) << 31) 29 #define CSTATE_WAKE_MASK_SHIFT ULL(32) 30 #define CSTATE_WAKE_MASK_CLEAR U(0xFFFFFFFF) 31 32 /******************************************************************************* 33 * Auto-CC3 control macros 34 ******************************************************************************/ 35 #define MCE_AUTO_CC3_FREQ_MASK U(0x1FF) 36 #define MCE_AUTO_CC3_FREQ_SHIFT U(0) 37 #define MCE_AUTO_CC3_VTG_MASK U(0x7F) 38 #define MCE_AUTO_CC3_VTG_SHIFT U(16) 39 #define MCE_AUTO_CC3_ENABLE_BIT (U(1) << 31) 40 41 /******************************************************************************* 42 * Macros for the 'IS_SC7_ALLOWED' command 43 ******************************************************************************/ 44 #define MCE_SC7_ALLOWED_MASK U(0x7) 45 #define MCE_SC7_WAKE_TIME_SHIFT U(32) 46 47 /******************************************************************************* 48 * Macros for 'read/write ctats' commands 49 ******************************************************************************/ 50 #define MCE_CSTATE_STATS_TYPE_SHIFT ULL(32) 51 #define MCE_CSTATE_WRITE_DATA_LO_MASK U(0xF) 52 53 /******************************************************************************* 54 * Macros for 'update crossover threshold' command 55 ******************************************************************************/ 56 #define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT U(32) 57 58 /******************************************************************************* 59 * MCA argument macros 60 ******************************************************************************/ 61 #define MCA_ARG_ERROR_MASK U(0xFF) 62 #define MCA_ARG_FINISH_SHIFT U(24) 63 #define MCA_ARG_FINISH_MASK U(0xFF) 64 65 /******************************************************************************* 66 * Uncore PERFMON ARI struct 67 ******************************************************************************/ 68 #define UNCORE_PERFMON_CMD_READ U(0) 69 #define UNCORE_PERFMON_CMD_WRITE U(1) 70 71 #define UNCORE_PERFMON_CMD_MASK U(0xFF) 72 #define UNCORE_PERFMON_CMD_SHIFT U(24) 73 #define UNCORE_PERFMON_UNIT_GRP_MASK U(0xF) 74 #define UNCORE_PERFMON_SELECTOR_MASK U(0xF) 75 #define UNCORE_PERFMON_REG_MASK U(0xFF) 76 #define UNCORE_PERFMON_CTR_MASK U(0xFF) 77 #define UNCORE_PERFMON_RESP_STATUS_MASK U(0xFF) 78 #define UNCORE_PERFMON_RESP_STATUS_SHIFT U(24) 79 80 /******************************************************************************* 81 * Structure populated by arch specific code to export routines which perform 82 * common low level MCE functions 83 ******************************************************************************/ 84 typedef struct arch_mce_ops { 85 /* 86 * This ARI request sets up the MCE to start execution on assertion 87 * of STANDBYWFI, update the core power state and expected wake time, 88 * then determine the proper power state to enter. 89 */ 90 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state, 91 uint32_t wake_time); 92 /* 93 * This ARI request allows updating of the CLUSTER_CSTATE, 94 * CCPLEX_CSTATE, and SYSTEM_CSTATE register values. 95 */ 96 int32_t (*update_cstate_info)(uint32_t ari_base, 97 uint32_t cluster, 98 uint32_t ccplex, 99 uint32_t system, 100 uint8_t sys_state_force, 101 uint32_t wake_mask, 102 uint8_t update_wake_mask); 103 /* 104 * This ARI request allows updating of power state crossover 105 * threshold times. An index value specifies which crossover 106 * state is being updated. 107 */ 108 int32_t (*update_crossover_time)(uint32_t ari_base, 109 uint32_t type, 110 uint32_t time); 111 /* 112 * This ARI request allows read access to statistical information 113 * related to power states. 114 */ 115 uint64_t (*read_cstate_stats)(uint32_t ari_base, 116 uint32_t state); 117 /* 118 * This ARI request allows write access to statistical information 119 * related to power states. 120 */ 121 int32_t (*write_cstate_stats)(uint32_t ari_base, 122 uint32_t state, 123 uint32_t stats); 124 /* 125 * This ARI request allows the CPU to understand the features 126 * supported by the MCE firmware. 127 */ 128 uint64_t (*call_enum_misc)(uint32_t ari_base, uint32_t cmd, 129 uint32_t data); 130 /* 131 * This ARI request allows querying the CCPLEX to determine if 132 * the CCx state is allowed given a target core C-state and wake 133 * time. If the CCx state is allowed, the response indicates CCx 134 * must be entered. If the CCx state is not allowed, the response 135 * indicates CC6/CC7 can't be entered 136 */ 137 int32_t (*is_ccx_allowed)(uint32_t ari_base, uint32_t state, 138 uint32_t wake_time); 139 /* 140 * This ARI request allows querying the CCPLEX to determine if 141 * the SC7 state is allowed given a target core C-state and wake 142 * time. If the SC7 state is allowed, all cores but the associated 143 * core are offlined (WAKE_EVENTS are set to 0) and the response 144 * indicates SC7 must be entered. If the SC7 state is not allowed, 145 * the response indicates SC7 can't be entered 146 */ 147 int32_t (*is_sc7_allowed)(uint32_t ari_base, uint32_t state, 148 uint32_t wake_time); 149 /* 150 * This ARI request allows a core to bring another offlined core 151 * back online to the C0 state. Note that a core is offlined by 152 * entering a C-state where the WAKE_MASK is all 0. 153 */ 154 int32_t (*online_core)(uint32_t ari_base, uint32_t cpuid); 155 /* 156 * This ARI request allows the CPU to enable/disable Auto-CC3 idle 157 * state. 158 */ 159 int32_t (*cc3_ctrl)(uint32_t ari_base, 160 uint32_t freq, 161 uint32_t volt, 162 uint8_t enable); 163 /* 164 * This ARI request allows updating the reset vector register for 165 * D15 and A57 CPUs. 166 */ 167 int32_t (*update_reset_vector)(uint32_t ari_base); 168 /* 169 * This ARI request instructs the ROC to flush A57 data caches in 170 * order to maintain coherency with the Denver cluster. 171 */ 172 int32_t (*roc_flush_cache)(uint32_t ari_base); 173 /* 174 * This ARI request instructs the ROC to flush A57 data caches along 175 * with the caches covering ARM code in order to maintain coherency 176 * with the Denver cluster. 177 */ 178 int32_t (*roc_flush_cache_trbits)(uint32_t ari_base); 179 /* 180 * This ARI request instructs the ROC to clean A57 data caches along 181 * with the caches covering ARM code in order to maintain coherency 182 * with the Denver cluster. 183 */ 184 int32_t (*roc_clean_cache)(uint32_t ari_base); 185 /* 186 * This ARI request reads/writes the Machine Check Arch. (MCA) 187 * registers. 188 */ 189 uint64_t (*read_write_mca)(uint32_t ari_base, 190 uint64_t cmd, 191 uint64_t *data); 192 /* 193 * Some MC GSC (General Security Carveout) register values are 194 * expected to be changed by TrustZone secure ARM code after boot. 195 * Since there is no hardware mechanism for the CCPLEX to know 196 * that an MC GSC register has changed to allow it to update its 197 * own internal GSC register, there needs to be a mechanism that 198 * can be used by ARM code to cause the CCPLEX to update its GSC 199 * register value. This ARI request allows updating the GSC register 200 * value for a certain carveout in the CCPLEX. 201 */ 202 int32_t (*update_ccplex_gsc)(uint32_t ari_base, uint32_t gsc_idx); 203 /* 204 * This ARI request instructs the CCPLEX to either shutdown or 205 * reset the entire system 206 */ 207 void (*enter_ccplex_state)(uint32_t ari_base, uint32_t state_idx); 208 /* 209 * This ARI request reads/writes data from/to Uncore PERFMON 210 * registers 211 */ 212 int32_t (*read_write_uncore_perfmon)(uint32_t ari_base, 213 uint64_t req, uint64_t *data); 214 /* 215 * This ARI implements ARI_MISC_CCPLEX commands. This can be 216 * used to enable/disable coresight clock gating. 217 */ 218 void (*misc_ccplex)(uint32_t ari_base, uint32_t index, 219 uint32_t value); 220 } arch_mce_ops_t; 221 222 /* declarations for ARI/NVG handler functions */ 223 int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 224 int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 225 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 226 uint8_t update_wake_mask); 227 int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 228 uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state); 229 int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 230 uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data); 231 int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 232 int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 233 int32_t ari_online_core(uint32_t ari_base, uint32_t core); 234 int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 235 int32_t ari_reset_vector_update(uint32_t ari_base); 236 int32_t ari_roc_flush_cache_trbits(uint32_t ari_base); 237 int32_t ari_roc_flush_cache(uint32_t ari_base); 238 int32_t ari_roc_clean_cache(uint32_t ari_base); 239 uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data); 240 int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx); 241 void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx); 242 int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, 243 uint64_t req, uint64_t *data); 244 void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value); 245 246 int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time); 247 int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, 248 uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, 249 uint8_t update_wake_mask); 250 int32_t nvg_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time); 251 uint64_t nvg_read_cstate_stats(uint32_t ari_base, uint32_t state); 252 int32_t nvg_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats); 253 int32_t nvg_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 254 int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time); 255 int32_t nvg_online_core(uint32_t ari_base, uint32_t core); 256 int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable); 257 258 extern void nvg_set_request_data(uint64_t req, uint64_t data); 259 extern void nvg_set_request(uint64_t req); 260 extern uint64_t nvg_get_result(void); 261 #endif /* MCE_PRIVATE_H */ 262