1/* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7#include <arch.h> 8#include <asm_macros.S> 9#include <bl_common.h> 10#include <context.h> 11#include <el3_common_macros.S> 12#include <smcc_helpers.h> 13#include <smcc_macros.S> 14 15 .globl bl1_vector_table 16 .globl bl1_entrypoint 17 18 /* ----------------------------------------------------- 19 * Setup the vector table to support SVC & MON mode. 20 * ----------------------------------------------------- 21 */ 22vector_base bl1_vector_table 23 b bl1_entrypoint 24 b report_exception /* Undef */ 25 b bl1_aarch32_smc_handler /* SMC call */ 26 b report_exception /* Prefetch abort */ 27 b report_exception /* Data abort */ 28 b report_exception /* Reserved */ 29 b report_exception /* IRQ */ 30 b report_exception /* FIQ */ 31 32 /* ----------------------------------------------------- 33 * bl1_entrypoint() is the entry point into the trusted 34 * firmware code when a cpu is released from warm or 35 * cold reset. 36 * ----------------------------------------------------- 37 */ 38 39func bl1_entrypoint 40/* --------------------------------------------------------------------- 41* If the reset address is programmable then bl1_entrypoint() is 42* executed only on the cold boot path. Therefore, we can skip the warm 43* boot mailbox mechanism. 44* --------------------------------------------------------------------- 45*/ 46 el3_entrypoint_common \ 47 _set_endian=1 \ 48 _warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \ 49 _secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \ 50 _init_memory=1 \ 51 _init_c_runtime=1 \ 52 _exception_vectors=bl1_vector_table 53 54 /* ----------------------------------------------------- 55 * Perform early platform setup & platform 56 * specific early arch. setup e.g. mmu setup 57 * ----------------------------------------------------- 58 */ 59 bl bl1_early_platform_setup 60 bl bl1_plat_arch_setup 61 62 /* ----------------------------------------------------- 63 * Jump to main function. 64 * ----------------------------------------------------- 65 */ 66 bl bl1_main 67 68 /* ----------------------------------------------------- 69 * Jump to next image. 70 * ----------------------------------------------------- 71 */ 72 73 /* 74 * MMU needs to be disabled because both BL1 and BL2 execute 75 * in PL1, and therefore share the same address space. 76 * BL2 will initialize the address space according to its 77 * own requirement. 78 */ 79 bl disable_mmu_icache_secure 80 stcopr r0, TLBIALL 81 dsb sy 82 isb 83 84 /* Get the cpu_context for next BL image */ 85 bl cm_get_next_context 86 87 /* Restore the SCR */ 88 ldr r2, [r0, #CTX_REGS_OFFSET + CTX_SCR] 89 stcopr r2, SCR 90 isb 91 92 /* 93 * Get the smc_context for next BL image, 94 * program the gp/system registers and exit 95 * secure monitor mode 96 */ 97 bl smc_get_next_ctx 98 smcc_restore_gp_mode_regs 99 eret 100endfunc bl1_entrypoint 101